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Hardware Accelerators for Data Sort in All Programmable Systems-on-ChipSKLYAROV, V. , SKLIAROVA, I.
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FPGA, system-on-chip, sorting, parallel processing, performance and resources evaluation
sorting(13), link(9), systems(8), programmable(7), zynq(6), networks(6), xilinx(5), sklyarov(5), skliarova(5), high(5)
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About this article
Date of Publication: 2015-11-30
Volume 15, Issue 4, Year 2015, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.04002
Web of Science Accession Number: 000368499800002
SCOPUS ID: 84949995957
The paper analyzes and evaluates architectures of the most efficient hardware accelerators for data sort in FPGA and all programmable systems-on-chip (such as devices from the Xilinx Zynq-7000 family). The following novel methods are proposed and discussed: 1) data sorting in hardware that is executed concurrently with getting inputs through single or multiple ports; 2) a technique allowing rational compromise between the cost and the latency of the circuit to be achieved. Both methods are targeted to hardware/software co-design and permit the best solution to be found for different requirements within pre-defined constraints. The results of experiments, implementations, and rigorous comparisons demonstrate high efficiency and broad applicability of the proposed methods for wide range of practical applications.
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 Digital design: Best practices and future trends, Sklyarov, V., Skliarova, I., 2016 15th Biennial Baltic Electronics Conference (BEC), ISBN 978-1-5090-1393-7, 2016.
Digital Object Identifier: 10.1109/BEC.2016.7743718 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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