| 3/2013 - 8 |
Rapid Prototyping of Sub-band Acoustic Echo Cancellers on FPGA PlatformsMURESAN, I.   , KIREI, B. S. , CONTAN, C. , TOPA, M. D. |
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Author keywords
acoustic echo cancellation, field programmable gate arrays, normalized least mean square filters, multi-rate signal processing, Xilinx system generator
References keywords
systems(14), adaptive(14), processing(13), signal(11), multi(9), fpga(9), echo(9), rate(8), implementation(8), design(8)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-08-31
Volume 13, Issue 3, Year 2013, On page(s): 45 - 50
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.03008
Web of Science Accession Number: 000326321600008
SCOPUS ID: 84884922053
Abstract
The paper focuses on a rapid prototyping technique of an acoustic echo canceller implemented on an FPGA platform. The goal is to reduce design, optimization and implementation cost and execution time. In complex signal processing applications, high-order adaptive filter structures suffer from decreased convergence speed and high computational complexity. The sub-band adaptive filtering technique is able to eliminate these disadvantages. The execution time of the echo cancellation in an acoustic enclosure is decreased using multi-rate digital signal processing. To speed-up the execution time of a common acoustic echo canceller, the sub-band decomposition of the source signal is proposed. Here, this procedure is implemented using the Xilinx System Generator library. The hardware implementation of the well-known NLMS adaptive algorithm was carried out. Moreover, the FIR filters in the analysis and synthesis banks are designed with the window method (using the Kaiser window), as the determination of the filter's coefficients is an important procedure to eliminate the alias. The alias occurs due to the usage of multi-rate systems. Hardware implementations that test the behavior of the proposed system were tested for nonstationary input signals. Results show superior tracking abilities of the designed system. Also, an estimation of the FPGA resources is established in each case. The ML501 Xilinx FPGA development board was used for its specific digital signal processing facilities. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
