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Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module PlacerHOO, C.-S. , JEEVAN, K. , GANAPATHY, V. , RAMIAH, H.
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design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization
design(14), systems(12), floorplanning(12), vlsi(8), representation(6), circuits(6), algorithm(6), aided(6), scale(5), optimization(5)
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About this article
Date of Publication: 2013-02-28
Volume 13, Issue 1, Year 2013, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.01002
Web of Science Accession Number: 000315768300002
SCOPUS ID: 84875343057
Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.
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 Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs, Hoo, Chyi-Shiang, Jeevan, Kanesan, Ramiah, Harikrishnan, International Journal of Circuit Theory and Applications, ISSN 0098-9886, Issue 3, Volume 43, 2015.
Digital Object Identifier: 10.1002/cta.1939 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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