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JCR Impact Factor: 0.650
JCR 5-Year IF: 0.639
Issues per year: 4
Current issue: Nov 2019
Next issue: Feb 2020
Avg review time: 72 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2019-Dec-16
Starting on the 15th of December 2019 all paper authors are required to enter their SCOPUS IDs. You may use the free SCOPUS ID lookup form to find yours in case you don't remember it.

2019-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

2018-May-31
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2018-Jun-27
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  1/2013 - 2

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

HOO, C.-S. See more information about HOO, C.-S. on SCOPUS See more information about HOO, C.-S. on IEEExplore See more information about HOO, C.-S. on Web of Science, JEEVAN, K. See more information about  JEEVAN, K. on SCOPUS See more information about  JEEVAN, K. on SCOPUS See more information about JEEVAN, K. on Web of Science, GANAPATHY, V. See more information about  GANAPATHY, V. on SCOPUS See more information about  GANAPATHY, V. on SCOPUS See more information about GANAPATHY, V. on Web of Science, RAMIAH, H. See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (565 KB) | Citation | Downloads: 653 | Views: 2,962

Author keywords
design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization

References keywords
design(14), systems(12), floorplanning(12), vlsi(8), representation(6), circuits(6), algorithm(6), aided(6), scale(5), optimization(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-02-28
Volume 13, Issue 1, Year 2013, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.01002
Web of Science Accession Number: 000315768300002
SCOPUS ID: 84875343057

Abstract
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Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.


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SCOPUS® Times Cited: 2
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Cited-By CrossRef

[1] Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs, Hoo, Chyi-Shiang, Jeevan, Kanesan, Ramiah, Harikrishnan, International Journal of Circuit Theory and Applications, ISSN 0098-9886, Issue 3, Volume 43, 2015.
Digital Object Identifier: 10.1002/cta.1939
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Faculty of Electrical Engineering and Computer Science
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