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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  1/2019 - 2

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

KIREI, B. S. See more information about KIREI, B. S. on SCOPUS See more information about KIREI, B. S. on IEEExplore See more information about KIREI, B. S. on Web of Science, CHEREJA, V.-I.-M. See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about CHEREJA, V.-I.-M. on Web of Science, HINTEA, S. See more information about  HINTEA, S. on SCOPUS See more information about  HINTEA, S. on SCOPUS See more information about HINTEA, S. on Web of Science, TOPA, M. D. See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on Web of Science
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Download PDF pdficon (1,250 KB) | Citation | Downloads: 541 | Views: 1,162

Author keywords
logic design, software libraries, power dissipation, logic gates, CMOS integrated circuits

References keywords
power(17), circuits(10), estimation(9), design(7), cmos(7), vhdl(6), systems(5), digital(5), vlsi(4), system(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-02-28
Volume 19, Issue 1, Year 2019, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.01002
Web of Science Accession Number: 000459986900002
SCOPUS ID: 85064200214

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In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates.

References | Cited By  «-- Click to see who has cited this paper

[1] M. Meixner, T. G. Noll, "Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 7, pp. 787-791, July 2017.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 3]

[2] M. Pedram, S. Nazarian, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods," Proceedings of the IEEE, vol. 94, no. 8, pp. 1487-1501, Aug. 2006.
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[CrossRef] [SCOPUS Times Cited 1]

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[6] C. H. Roth, L. K. John, "Digital System Design Using VHDL", Thomson Learning, Toronto, Canada, 2008.

[7] M. Pedram, "Power Simulation and Estimation in VLSI Circuits", In The "VLSI Handbook", Edited by W-K. Chen, The CRC Press and the IEEE Press, 1999

[8] S. Orcioni, M. Giammarini, C. Scavongelli, G. B. Vece, M. Conti, "Energy estimation in SystemC with Powersim," Integration, vol. 55, 2016, pp. 118-128,
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 7]

[9] R. Bevaart, N. Dumitru, R. Nouta, "VHDL Power estimation of CMOS Logic Cells", Proceedings - ProRISC CSSP97, Workshop on Circuits, Systems and Signal Processing, Mierlo, the Netherlands, November 27 - 28, 1997

[10] L. Kruse, D. Rabe, W. Nebel, "VHDL Power Simulator: Power Analysis at Gate-Level" In: Kloos C.D., Cerny E. (eds) Hardware Description Languages and their Applications. IFIP - The International Federation for Information Processing. Springer, Boston, MA, 1997. pp. 317-333,

[11] I. Chiuchisan, A. D. Potorac, A. Graur, "Finite State Machine Design and VHDL Coding Techniques", 10th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 27-29, 2010

[12] S. Zhou and J. Bian, "Partition-based Retiming and Precomputation for Dynamic Power Reduction," 2006 International Conference on Communications, Circuits and Systems, Guilin, China, 2006.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 3]

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[CrossRef] [SCOPUS Times Cited 1]

[14] V. Chereja, A. I. Potarniche, S. A. Ranga, B. S. Kirei, M. D. Topa, "Power Dissipation Estimation of CMOS Digital Circuits at the Gate Level in VHDL", Proceedings of International Symposium on Electronics and Telecommunications Conference, Timisoara, Romania, 7-9 Nov. 2018

[15] A. Chandrakasan, R. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers Norwell, MA, USA,1995

[16] S. Ghissoni, J. B. Martins, L. L. Oliveira, "A new methodology in power estimation in CMOS combinational circuits at logic level," 48th Midwest Symposium on Circuits and Systems, 2005., Covington, KY, 2005, pp. 1251-1254 Vol. 2.
[CrossRef] [SCOPUS Times Cited 1]

[17] Texas Instruments, "CMOS Power Consumption and Cpd Calculation", Application Note, June 1997

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[19] HAMEG Instruments, "Power Supply HM7042-2 Manual", 2004

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[CrossRef] [Web of Science Times Cited 231] [SCOPUS Times Cited 299]

[21] T. Sakurai, "Low power digital circuit design," Proceedings of the 30th European Solid-State Circuits Conference 2004, Leuven, Belgium, 23-23 Sept. 2004.

[22] M. Meixner, T. G. Noll, "Limits of gate-level power estimation considering real delay effects and glitches," 2014 International Symposium on System-on-Chip (SoC), Tampere, pp. 1-7, 2014.
[CrossRef] [SCOPUS Times Cited 4]

[23] M. C. Hansen, H. Yalcin, J. P. Hayes, "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering", IEEE Design & Test, Vol. 16, Iss. 3, pg. 72-80, July 1999.
[CrossRef] [Web of Science Times Cited 216] [SCOPUS Times Cited 289]

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References Weight

Web of Science® Citations for all references: 700 TCR
SCOPUS® Citations for all references: 905 TCR

Web of Science® Average Citations per reference: 28 ACR
SCOPUS® Average Citations per reference: 36 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2021-03-05 16:27 in 80 seconds.

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