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JCR Impact Factor: 0.595
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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

2017-Jan-30
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2016-Dec-17
IoT is a new emerging technology domain which will be used to connect all objects through the Internet for remote sensing and control. IoT uses a combination of WSN (Wireless Sensor Network), M2M (Machine to Machine), robotics, wireless networking, Internet technologies, and Smart Devices. We dedicate a special section of Issue 2/2017 to IoT. Prospective authors are asked to make the submissions for this section no later than the 31st of March 2017, placing "IoT - " before the paper title in OpenConf.

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  1/2017 - 5

Efficient FPGA Implementation of High-Throughput Mixed Radix Multipath Delay Commutator FFT Processor for MIMO-OFDM

DALI, M., GUESSOUM, A. See more information about  GUESSOUM, A. on SCOPUS See more information about  GUESSOUM, A. on SCOPUS See more information about GUESSOUM, A. on Web of Science, GIBSON, R. M. See more information about  GIBSON, R. M. on SCOPUS See more information about  GIBSON, R. M. on SCOPUS See more information about GIBSON, R. M. on Web of Science, AMIRA, A. See more information about  AMIRA, A. on SCOPUS See more information about  AMIRA, A. on SCOPUS See more information about AMIRA, A. on Web of Science, RAMZAN, N. See more information about RAMZAN, N. on SCOPUS See more information about RAMZAN, N. on SCOPUS See more information about RAMZAN, N. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,687 KB) | Citation | Downloads: 168 | Views: 239

Author keywords
fast fourier transform, field programmable gate arrays, mimo, ofdm, parallel architecture

References keywords
systems(18), processor(11), ofdm(10), mimo(7), circuits(7), vlsi(6), very(6), tvlsi(6), scale(6), large(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 27 - 38
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01005
Web of Science Accession Number: 000396335900005

Abstract
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This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively.


References | Cited By  «-- Click to see who has cited this paper

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References Weight

Web of Science® Citations for all references: 3,584 TCR
SCOPUS® Citations for all references: 5,332 TCR

Web of Science® Average Citations per reference: 143 ACR
SCOPUS® Average Citations per reference: 213 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-06-27 13:07 in 179 seconds.




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