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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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Genetic Synthesis of New Reversible/Quantum Ternary Comparator, DEIBUK, V., BILOSHYTSKYI, A.
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Analysis of Real Overvoltage Disturbances by Using Nonstationary Signal Processing Techniques, VUJOSEVIC, S., MUJOVIC, S., DAKOVIC, M.
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Maximum Entropy Principle in Image Restoration, PETROVICI, M.-A., DAMIAN, C., COLTUC, D.
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Clarivate Analytics published the InCites Journal Citations Report for 2017. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.699, and the JCR 5-Year Impact Factor is 0.674.

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With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

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  1/2016 - 13

Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

NIMARA, S. See more information about NIMARA, S. on SCOPUS See more information about NIMARA, S. on IEEExplore See more information about NIMARA, S. on Web of Science, AMARICAI, A. See more information about  AMARICAI, A. on SCOPUS See more information about  AMARICAI, A. on SCOPUS See more information about AMARICAI, A. on Web of Science, BONCALO, O. See more information about  BONCALO, O. on SCOPUS See more information about  BONCALO, O. on SCOPUS See more information about BONCALO, O. on Web of Science, POPA, M. See more information about POPA, M. on SCOPUS See more information about POPA, M. on SCOPUS See more information about POPA, M. on Web of Science
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,191 KB) | Citation | Downloads: 299 | Views: 1,145

Author keywords
digital circuits, probabilistic circuits, register transfer level, reliability, simulated fault injection

References keywords
fault(14), test(10), design(10), level(8), circuits(8), injection(7), systems(6), probabilistic(6), vlsi(5), vhdl(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 93 - 98
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01013
Web of Science Accession Number: 000376995400013
SCOPUS ID: 84960108449

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This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit - the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.

References | Cited By  «-- Click to see who has cited this paper

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[2] B. E. S. Akgul, L. N. Chakrapani, P. Korkmaz, K.V. Palem, "Probabilistic CMOS Technology: A Survey and Future Directions" Proc. 2006 IFIP Int. Conf. on Very Large Scale Integration, 2006, pp. 1-6,
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[7] J. C. Baraza, J. Gracia, D. Gil, P.J. Gil, "Improvement of Fault Injection Techniques based on VHDL Code Modification", Proc. 10th IEEE International High-Level Design Validation and Test Workshop, 2005, pp. 19-26,
[CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 36]

[8] J. C. Baraza, J. Gracia, S. Blanc, D. Gil, P.J. Gil "Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code" IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol. 16, Issue 6, 2008, pp. 683-706,
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[9] J. Chen, C. Spagnol, S Grandhi, E Popovici, S. Cotofana, A Amaricai "Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits" Proc. 2014 IEEE Annual Symp. On VLSI (ISVLSI), 2014, pp. 380-385,
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[10] M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, et al. "Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis" Proc. 2011 Design Automation and Test in Europe (DATE), 2011, pp. 1-4,

[11] A. Amaricai, S. Nimara, O. Boncalo, J. Chen, E. Popovici "Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits", Proc. 17th Euromicro Digital System Design, 2014, pp. 473-479,
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[12] S. Nimara, A. Amaricai, O. Boncalo, M. Popa "Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects" Proc. 10th Conf. on PhD Research in Microelectronics (PRIME), 2014, pp. 1-4,

[13] S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level", Proc. International Test Conference (ITC), 2003,

[14] N. Bombieri, F. Fummi, V. Guarnieri, "Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction", Proc 16th European Test Symposium (ETS), 2011,
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[15] P. A. Thaker, "Register-Transfer Level Fault Modeling and Test Evaluation Technique for VLSI Circuits", Proc. International Test Conference (ITC), 2000,
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[16] M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, "Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller", Proc 27th IEEE VLSI Test Symposium, 2009,
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[17] A. Evans, D. Alexandrescu, E. Costenaro, L. Chen "Hierarchical RTL-Based Combinatorial SER Estimation", Proc. 19th Int. On-Line Testing Symp. (IOLTS), 2013, pp. 139-144,
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[18] M. Sonza Reorda, M. Violante "Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments" Proc. 17th IEEE Symp on Defect and Fault Tolerance in VLSI Systems (DFT), 2002, pp. 263-271,
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[19] G. B. Hamad, O. Mohamed, Y. Savaria "Probabilistic model checking of single event transient propagation at RTL level" Proc. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 471-475,
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[20] N. Foutris, M. Kaliorakis, S. Tselonis, D. Gizopoulos "Versatile architecture-level fault injection framework for reliability evaluation: A first report" Proc. 20th Int. On-Line Testing Symp. (IOLTS), 2014,
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[21] M. Weiner, B. Nikolic, Z. Zhang " LDPC Decoder Architecture for High-Data Rate Personal-Area Networks", Proc. Int. Symp on Circuits and Systems (ISCAS), 2011, pp. 1784 - 1787,
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[22] Y. S. Park, D. Blaauw, D. Sylvester, Z. Zhang, "Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM", IEEE Journal of Solid State Circuits, Vol. 49, Issue 3, 2014, pp. 783-794,
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[23] 128-bit AES crypto-chip Verilog design, [Online] Available: Temporary on-line reference link removed - see the PDF document

[24] D. K. Pradhan Fault-Tolerant Computer System Design, Prentice Hall, 1997

[25] C.-C. Lu, S.-Y. Tseng, "Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter" Proc. IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP), 2002, pp. 277-285,
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 78]

References Weight

Web of Science® Citations for all references: 256 TCR
SCOPUS® Citations for all references: 614 TCR

Web of Science® Average Citations per reference: 10 ACR
SCOPUS® Average Citations per reference: 24 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-10-18 19:59 in 166 seconds.

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