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Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit DescriptionsNIMARA, S. , AMARICAI, A. , BONCALO, O. , POPA, M.
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digital circuits, probabilistic circuits, register transfer level, reliability, simulated fault injection
fault(14), test(10), design(10), level(8), circuits(8), injection(7), systems(6), probabilistic(6), vlsi(5), vhdl(4)
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About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 93 - 98
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01013
Web of Science Accession Number: 000376995400013
SCOPUS ID: 84960108449
This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit - the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.
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| P. Korkmaz, B. E. S Akgul, K. Palem "Energy, Performance, and Probability Tradeoffs for Energy-Efficient Probabilistic CMOS Circuits" IEEE Trans. On Circuits and Systems I, vol. 55, Issue 8, 2008, |
[CrossRef] [Web of Science Times Cited 25]
 B. E. S. Akgul, L. N. Chakrapani, P. Korkmaz, K.V. Palem, "Probabilistic CMOS Technology: A Survey and Future Directions" Proc. 2006 IFIP Int. Conf. on Very Large Scale Integration, 2006, pp. 1-6,
 K. V. Palem, "Energy aware computing through probabilistic switching: A study of limits", IEEE Trans. on Computers, Vol. 54, Issue 9, 2005, pp. 1123-1137,
[CrossRef] [Web of Science Times Cited 87]
 V. De "Near-Threshold Voltage design in nanoscale CMOS", Proc 2013 Design Automation & Test in Europe (DATE), 2013, pp. 612-615,
 H. Khaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Bokhar "Near Threshold Voltage Design: Opportunities and Challenges" Proc. Design Automation Conference (DAC), 2012, pp. 1153-1158,
 E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson "Fault Injection into VHDL Models: The MEFISTO Tool", Proc. 24th Annual International Symposium on Fault Tolerant Computing (FTCS-24), 1994, pp 66-75,
 J. C. Baraza, J. Gracia, D. Gil, P.J. Gil, "Improvement of Fault Injection Techniques based on VHDL Code Modification", Proc. 10th IEEE International High-Level Design Validation and Test Workshop, 2005, pp. 19-26,
[CrossRef] [Web of Science Times Cited 16]
 J. C. Baraza, J. Gracia, S. Blanc, D. Gil, P.J. Gil "Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code" IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol. 16, Issue 6, 2008, pp. 683-706,
[CrossRef] [Web of Science Times Cited 45]
 J. Chen, C. Spagnol, S Grandhi, E Popovici, S. Cotofana, A Amaricai "Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits" Proc. 2014 IEEE Annual Symp. On VLSI (ISVLSI), 2014, pp. 380-385,
[CrossRef] [Web of Science Times Cited 1]
 M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, et al. "Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis" Proc. 2011 Design Automation and Test in Europe (DATE), 2011, pp. 1-4,
 A. Amaricai, S. Nimara, O. Boncalo, J. Chen, E. Popovici "Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits", Proc. 17th Euromicro Digital System Design, 2014, pp. 473-479,
[CrossRef] [Web of Science Times Cited 8]
 S. Nimara, A. Amaricai, O. Boncalo, M. Popa "Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects" Proc. 10th Conf. on PhD Research in Microelectronics (PRIME), 2014, pp. 1-4,
 S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level", Proc. International Test Conference (ITC), 2003,
 N. Bombieri, F. Fummi, V. Guarnieri, "Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction", Proc 16th European Test Symposium (ETS), 2011,
[CrossRef] [Web of Science Times Cited 4]
 P. A. Thaker, "Register-Transfer Level Fault Modeling and Test Evaluation Technique for VLSI Circuits", Proc. International Test Conference (ITC), 2000,
[CrossRef] [Web of Science Times Cited 19]
 M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, "Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller", Proc 27th IEEE VLSI Test Symposium, 2009,
[CrossRef] [Web of Science Times Cited 3]
 A. Evans, D. Alexandrescu, E. Costenaro, L. Chen "Hierarchical RTL-Based Combinatorial SER Estimation", Proc. 19th Int. On-Line Testing Symp. (IOLTS), 2013, pp. 139-144,
 M. Sonza Reorda, M. Violante "Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments" Proc. 17th IEEE Symp on Defect and Fault Tolerance in VLSI Systems (DFT), 2002, pp. 263-271,
[CrossRef] [Web of Science Times Cited 10]
 G. B. Hamad, O. Mohamed, Y. Savaria "Probabilistic model checking of single event transient propagation at RTL level" Proc. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 471-475,
 N. Foutris, M. Kaliorakis, S. Tselonis, D. Gizopoulos "Versatile architecture-level fault injection framework for reliability evaluation: A first report" Proc. 20th Int. On-Line Testing Symp. (IOLTS), 2014,
 M. Weiner, B. Nikolic, Z. Zhang " LDPC Decoder Architecture for High-Data Rate Personal-Area Networks", Proc. Int. Symp on Circuits and Systems (ISCAS), 2011, pp. 1784 - 1787,
 Y. S. Park, D. Blaauw, D. Sylvester, Z. Zhang, "Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM", IEEE Journal of Solid State Circuits, Vol. 49, Issue 3, 2014, pp. 783-794,
[CrossRef] [Web of Science Times Cited 36]
 128-bit AES crypto-chip Verilog design, [Online] Available: Temporary on-line reference link removed - see the PDF document
 D. K. Pradhan Fault-Tolerant Computer System Design, Prentice Hall, 1997
 C.-C. Lu, S.-Y. Tseng, "Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter" Proc. IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP), 2002, pp. 277-285,
[CrossRef] [Web of Science Times Cited 23]
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