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JCR Impact Factor: 0.800
JCR 5-Year IF: 1.000
SCOPUS CiteScore: 2.0
Issues per year: 4
Current issue: Feb 2024
Next issue: May 2024
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

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2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  3/2015 - 2

Instruction-level Real-time Secure Processor Using an Error Correction Code

YOON, S. M. See more information about YOON, S. M. on SCOPUS See more information about YOON, S. M. on IEEExplore See more information about YOON, S. M. on Web of Science, LEE, S. W. See more information about  LEE, S. W. on SCOPUS See more information about  LEE, S. W. on SCOPUS See more information about LEE, S. W. on Web of Science, PARK, J. K. See more information about  PARK, J. K. on SCOPUS See more information about  PARK, J. K. on SCOPUS See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
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Download PDF pdficon (1,146 KB) | Citation | Downloads: 831 | Views: 2,812

Author keywords
secure processor, security, instruction, correlation, chain

References keywords
security(5), systems(4), secure(4), execution(4), efficient(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-08-31
Volume 15, Issue 3, Year 2015, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.03002
Web of Science Accession Number: 000360171500002
SCOPUS ID: 84940746882

Abstract
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In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area.


References | Cited By  «-- Click to see who has cited this paper

[1] M. L. Pollar, F. Martinelli and D. Sgandurra, "A Survey on Security for Mobile Devices," IEEE Comm. Surveys and Tutorials, Vol.15, No.1, pp.446-471, 2013.
[CrossRef] [Web of Science Times Cited 276]


[2] K. Nikita, "Security and Privacy in Biomedical Telemetry: Mobile Health Platform for Secure Information Exchange," Wiley-IEEE Press eBook Chapters, 2014.
[CrossRef]


[3] S. Ravi, A. Raghunathan, P. Kocher, and S. Hattangady, "Security in Embedded Systems: Design Challenges," ACM Trans. on Embedded Computing Systems, Vol. 3, pp. 461-491, 2004.
[CrossRef]


[4] A. Murat Fiskiran, Ruby B. Lee "Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution" ICCD, 2004.
[CrossRef] [Web of Science Times Cited 36]


[5] T. Maude and D. Maude, "Hardware Protection Against Software Piracy", Communications of the ACM, vol. 27, no. 9, pp.950-959, 1984.
[CrossRef] [Web of Science Times Cited 22]


[6] D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell and M. Horowitz, "Architectural Support for Copy and Tamper Resistant Software", Proc. of ASPLOS, pp. 168-177, 2000.
[CrossRef]


[7] V. Kiriansky, D. Bruening, and S. Amarasinghe, "Secure Execution via Program Sheperding," Proc. of 11th USENIX Security Symp., pp.191-206, 2002.

[8] D. L. Detlefs, K. Leino, G. Nelson, and J. Saxe, "Extended static checking," Tech. rep., Systems Research Center, Compaq Inc., pp.1-44, 1998.

[9] S. W. Lee and J. T. Kim, "Instruction Level Tampering Detection Technique using Error Detection Code for Embedded Systems," Proc. of ICCMSE, Vol. 1, pp.1-4. 2005.

[10] W. Arbaugh, D. Farber, and J. Smith. "A secure and reliable bootstrap architecture" Proc. of IEEE Symp. on Security, pp.65-71, 1997.
[CrossRef] [Web of Science Times Cited 174]


[11] G. E. Suh, D. Clarke, B. Gassend, M. V. Dijk, S. Devadas, "Efficient Memory Integrity Verification and Encryption for Secure Processors", Proc. of IEEE/ACM Int'l. Sym. on MICRO, pp. 339-350, 2003.
[CrossRef]


[12] J. P. McGregor, D. K. Karig, Z.Shi, and Ruby B. Lee, "A Processor Architecture Defense against Buffer Overflow Attacks", Proc. of IEEE Int'l. Conf. ITRE, pp. 243-250, 2003.
[CrossRef] [Web of Science Times Cited 35]


[13] B. Gassend, G. E. Suh, D. Clarke, M. V. Dijk, and S. Devadas, "Caches and Hash Trees for Efficient Memory Integrity Verification", Proc. of Int'l Symp. on HPCA, pp.295-306, 2003.
[CrossRef] [Web of Science Times Cited 118]


[14] S. T. J. Fenn, M. Benaissa, and D. Taylor, "Bit-serial Berlekamp-like multipliers for GF(2m)," Electronics Letters, Vol. 31, 1995, pp. 1893-1894,
[CrossRef] [Web of Science Times Cited 6]


[15] I. S. Reed and X. Chen, "Error-Control Coding for Data Network," Kluwer Academic Publishers, 1999.

[16] S. W. Lee, J.T. Kim and J-S. Cha, "Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device," LNCS, Vol. 3681, 2005.
[CrossRef]


[17] F-X. Standaert, G. Rouvroy, J-J. Quisquater, and J-D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," LNCS, vol.2779, pp. 334-350, 2003.
[CrossRef]


[18] G. P. Saggese, A. Mazzeo, N. Mazzocca, and A.G.M. Strollo, "An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm," LNCS, vol.2778, pp.292-302, 2003.
[CrossRef]


[19] S-S. Wang, and W-S. Ni, "An Efficient FPGA Implementation of Advanced Encryption Standard Algorithm," Proc. of ISCAS 2004, Vol. 2, pp. 597-600, 2004.
[CrossRef]


[20] W. Shi, H-H. S. Lee, C. Lu, and M. Ghosh. "Towards the Issues in Architectural Support for Protection of Software Execution." Proc. of ASPLOS, pp.1-10, 2004.
[CrossRef]




References Weight

Web of Science® Citations for all references: 667 TCR
SCOPUS® Citations for all references: 0

Web of Science® Average Citations per reference: 32 ACR
SCOPUS® Average Citations per reference: 0

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-03-18 19:08 in 91 seconds.




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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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