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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

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  3/2015 - 2

Instruction-level Real-time Secure Processor Using an Error Correction Code

YOON, S. M. See more information about YOON, S. M. on SCOPUS See more information about YOON, S. M. on IEEExplore See more information about YOON, S. M. on Web of Science, LEE, S. W. See more information about  LEE, S. W. on SCOPUS See more information about  LEE, S. W. on SCOPUS See more information about LEE, S. W. on Web of Science, PARK, J. K. See more information about  PARK, J. K. on SCOPUS See more information about  PARK, J. K. on SCOPUS See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,146 KB) | Citation | Downloads: 380 | Views: 1,339

Author keywords
secure processor, security, instruction, correlation, chain

References keywords
security(5), systems(4), secure(4), execution(4), efficient(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-08-31
Volume 15, Issue 3, Year 2015, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.03002
Web of Science Accession Number: 000360171500002
SCOPUS ID: 84940746882

Abstract
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In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [SCOPUS Times Cited 3]


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[CrossRef] [SCOPUS Times Cited 281]


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[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 30]


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[CrossRef] [Web of Science Times Cited 17] [SCOPUS Times Cited 23]


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[CrossRef]


[7] V. Kiriansky, D. Bruening, and S. Amarasinghe, "Secure Execution via Program Sheperding," Proc. of 11th USENIX Security Symp., pp.191-206, 2002.

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[CrossRef] [Web of Science Times Cited 102]


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[CrossRef] [SCOPUS Times Cited 91]


[12] J. P. McGregor, D. K. Karig, Z.Shi, and Ruby B. Lee, "A Processor Architecture Defense against Buffer Overflow Attacks", Proc. of IEEE Int'l. Conf. ITRE, pp. 243-250, 2003.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 44]


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[CrossRef] [Web of Science Times Cited 39] [SCOPUS Times Cited 140]


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[16] S. W. Lee, J.T. Kim and J-S. Cha, "Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device," LNCS, Vol. 3681, 2005.
[CrossRef]


[17] F-X. Standaert, G. Rouvroy, J-J. Quisquater, and J-D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," LNCS, vol.2779, pp. 334-350, 2003.
[CrossRef]


[18] G. P. Saggese, A. Mazzeo, N. Mazzocca, and A.G.M. Strollo, "An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm," LNCS, vol.2778, pp.292-302, 2003.
[CrossRef]


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[CrossRef] [SCOPUS Times Cited 24]


[20] W. Shi, H-H. S. Lee, C. Lu, and M. Ghosh. "Towards the Issues in Architectural Support for Protection of Software Execution." Proc. of ASPLOS, pp.1-10, 2004.
[CrossRef]




References Weight

Web of Science® Citations for all references: 351 TCR
SCOPUS® Citations for all references: 865 TCR

Web of Science® Average Citations per reference: 17 ACR
SCOPUS® Average Citations per reference: 41 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-04-18 04:19 in 122 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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