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JCR Impact Factor: 0.459
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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 644266260
doi: 10.4316/AECE


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  1/2015 - 14

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

KAZMI, M. See more information about KAZMI, M. on SCOPUS See more information about KAZMI, M. on IEEExplore See more information about KAZMI, M. on Web of Science, AZIZ, A. See more information about  AZIZ, A. on SCOPUS See more information about  AZIZ, A. on SCOPUS See more information about AZIZ, A. on Web of Science, AKHTAR, P. See more information about  AKHTAR, P. on SCOPUS See more information about  AKHTAR, P. on SCOPUS See more information about AKHTAR, P. on Web of Science, KUNDI, D.-S. See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on Web of Science
 
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Download PDF pdficon (780 KB) | Citation | Downloads: 247 | Views: 1,164

Author keywords
buffer storage, convolver, field programmable gate array, image processing, image storage

References keywords
processing(15), fpga(13), systems(11), image(11), time(10), real(10), implementation(7), design(7), vision(6), hardware(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 95 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01014
Web of Science Accession Number: 000352158600014
SCOPUS ID: 84924812669

Abstract
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Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs) are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA) based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs) implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs) are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU). Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps). Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.


References | Cited By  «-- Click to see who has cited this paper

[1] C. T. Huitzil, M. A. Estrada, "Real-time image processing with a compact FPGA-based systolic architecture," Real-Time Imaging, vol. 10, no. 3, pp. 177-187, June. 2004, [CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 36]

[2] H. Zhang, M. Xia, G. Hu, "A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.54, no.2, pp.200-204, Feb. 2007,
[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 23]


[3] Q. Liu, G.A. Constantinides,K. Masselos, P. Cheung, "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.28, no.3, pp.305-315, March 2009,
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 8]


[4] D. G. Bailey, "Design for embedded image processing on FPGAs", pp. 116, 233, John Wiley & Sons, 2011.

[5] B. Bosi, G. Bois, Y. Savaria, "Reconfigurable pipelined 2-D convolvers for fast digital signal processing," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.7, no.3, pp.299-308, Sept. 1999,
[CrossRef] [Web of Science Times Cited 53] [SCOPUS Times Cited 68]


[6] X. Liang, J. Jean, K. Tomko, "Data buffering and allocation in mapping generalized template matching on reconfigurable systems," The Journal of Supercomputing, vol. 19, no. 1, pp. 77-91, 2001,
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 22]


[7] K. Wiatr, E. Jamro, "Implementation image data convolutions operations in FPGA reconfigurable structures for real-time vision systems," Information Technology: Coding and Computing, 2000. Proceedings. International Conference on, pp.152-157, 2000,
[CrossRef] [SCOPUS Times Cited 9]


[8] F. C. Tormo, P. L. Molinet, "Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.53, no.2, pp.105-109, Feb. 2006,
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 26]


[9] T. P. Cao, D. Elton, G. Deng, "Fast buffering for FPGA implementation of vision-based object recognition systems," Journal of Real-Time Image Processing, vol. 7, no. 3, pp. 173-183, 2012,
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 4]


[10] M. Schmidt, M. Reichenbach, A. Loos, D. Fey, " A smart camera processing pipeline for image applications utilizing Marching Pixels," Signal & Image Processing: An International Journal (SIPIJ), vol. 2, no. 3, pp. 137-156, 2011.

[11] C. T. Moore, H. Devos, D. Stroobandt, " Optimizing the FPGA memory design for a sobel edge detector," in 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2009), STW Technology Foundation, 2009, [Handle]

[12] C. L. Sotiropoulou, L. Voudouris, C. Gentsos, A. M. Demiris, N. Vassiliadis, S. Nikolaidis, "Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips," Biomedical Circuits and Systems, IEEE Transactions on , vol.8, no.2, pp.268-277, April 2014,
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 1]


[13] D. Koukounis, C. Ttofis, A. Papadopoulos, T. Theocharides, "A high performance hardware architecture for portable, low-power retinal vessel segmentation," Integration, the VLSI Journal, vol. 47, no. 3, pp. 377-386, June. 2014,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 2]


[14] D. Koukounis, C. Tttofis, T. Theocharides,"Hardware acceleration of retinal blood vasculature segmentation," In Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI '13), ACM, New York, NY, USA,pp. 113-118, 2013,
[CrossRef] [SCOPUS Times Cited 2]


[15] T. R. Savarimuthu, A. Kjær-Nielsen, A.S. Sørensen," Real-time medical video processing, enabled by hardware accelerated correlations," Journal of Real-Time Image Processing, vol. 6, no. 3, pp. 187-197, 2011,
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 11]


[16] R. M. Gibson, A. Ahmadinia, S.G. McMeekin, N.C. Strang, G. Morison, "A reconfigurable real-time morphological system for augmented vision," EURASIP Journal on Advances in Signal Processing, vol. 1, pp. 1-13, 2013,
[CrossRef] [Web of Science Times Cited 3]


[17] M. Imran, K. Khursheed, N. Ahmad, M. O'Nils, N. Lawal, M. A. Waheed, "Complexity Analysis of Vision Functions for Comparison of Wireless Smart Cameras," International Journal of Distributed Sensor Networks, vol. 2014, Article ID 710685, 15 pages, 2014,
[CrossRef] [Web of Science Record] [SCOPUS Times Cited 3]


[18] S. Jin, J. Cho, X. D. Pham, K. M. Lee, S. K. Park, M. Kim, J. W. Jeon, "FPGA Design and Implementation of a Real-Time Stereo Vision System," Circuits and Systems for Video Technology, IEEE Transactions on, vol.20, no.1, pp.15-26, Jan. 2010,
[CrossRef] [Web of Science Times Cited 92] [SCOPUS Times Cited 143]


[19] 7 Series FPGAs Memory Resources, User Guide, v1.10 .1, May2014, [Online] Available: Temporary on-line reference link removed - see the PDF document

[20] D. G. Bailey, "Efficient implementation of greyscale morphological filters," Field-Programmable Technology (FPT), 2010 International Conference on, pp.421-424, 8-10 Dec. 2010,
[CrossRef] [SCOPUS Times Cited 2]


[21] Virtex-5 FPGA, User Guide, v5.4, 2012, [Online] Available: Temporary on-line reference link removed - see the PDF document

[22] S. Singh, A.K. Saini, R. Saini, A. S. Mandal, C. Shekhar, A. Vohra,"A Novel Real-time Resource Efficient Implementation of Sobel Operator based Edge Detection on FPGA,". International Journal of Electronics, pp. 1-11, 2014,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 2]


[23] F.C. Tormo, P.L. Molinet, "Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing," Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on, pp.209-213, 2-4 Nov. 2005,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 6]


[24] S. Singh, S. Saurav, R. Saini, A .K. Saini, C. Shekhar, A. Vohra, "Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector," ISRN Electronics, vol. 2014, Article ID 857912, 9 pages, 2014,
[CrossRef]


[25] P. Turcza, M. Duplaga, "Hardware-Efficient Low-Power Image Processing System for Wireless Capsule Endoscopy," Biomedical and Health Informatics, IEEE Journal of , vol.17, no.6, pp.1046-1056, Nov. 2013, [CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 13]

[26] Logi CORE IP Block Memory Generator, Xilinx, v7.3. 2012, [Online] Available: Temporary on-line reference link removed - see the PDF document

[27] D. Chen, J. Cong, P. Pan, "FPGA Design Automation: A Survey," Found. Trends Electron. Des. Autom, vol. 1, no. 3, pp, 139-169, January. 2006,
[CrossRef] [SCOPUS Times Cited 45]


[28] N. P. Sedcole, "Reconfigurable platform-based design in FPGAs for video image processing." PhD diss., University of London, 2006.



References Weight

Web of Science® Citations for all references: 248 TCR
SCOPUS® Citations for all references: 426 TCR

Web of Science® Average Citations per reference: 9 ACR
SCOPUS® Average Citations per reference: 15 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2016-12-02 06:37 in 114 seconds.




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