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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 644266260
doi: 10.4316/AECE


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  3/2014 - 16

Embedded Processor Oriented Compiler Infrastructure

DJUKIC, M. See more information about DJUKIC, M. on SCOPUS See more information about DJUKIC, M. on IEEExplore See more information about DJUKIC, M. on Web of Science, POPOVIC, M. See more information about  POPOVIC, M. on SCOPUS See more information about  POPOVIC, M. on SCOPUS See more information about POPOVIC, M. on Web of Science, CETIC, N. See more information about  CETIC, N. on SCOPUS See more information about  CETIC, N. on SCOPUS See more information about CETIC, N. on Web of Science, POVAZAN, I. See more information about POVAZAN, I. on SCOPUS See more information about POVAZAN, I. on SCOPUS See more information about POVAZAN, I. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,079 KB) | Citation | Downloads: 225 | Views: 1,357

Author keywords
digital signal processors, embedded software, fixed-point arithmetic, software tools

References keywords
embedded(12), systems(10), compiler(10), code(10), optimization(7), design(7), compilers(6), processors(5), generation(5), sigplan(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-08-31
Volume 14, Issue 3, Year 2014, On page(s): 123 - 130
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.03016
Web of Science Accession Number: 000340869800016
SCOPUS ID: 84907337455

Abstract
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In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.


References | Cited By  «-- Click to see who has cited this paper

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References Weight

Web of Science® Citations for all references: 121 TCR
SCOPUS® Citations for all references: 377 TCR

Web of Science® Average Citations per reference: 3 ACR
SCOPUS® Average Citations per reference: 11 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2016-12-09 20:10 in 145 seconds.




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