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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
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ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  2/2019 - 5

Immunity Characterization of FPGA I/Os for Fault-Tolerant Circuit Designs against EMI

NGUYEN, V. T. See more information about NGUYEN, V. T. on SCOPUS See more information about NGUYEN, V. T. on IEEExplore See more information about NGUYEN, V. T. on Web of Science, DAM, M. T. See more information about  DAM, M. T. on SCOPUS See more information about  DAM, M. T. on SCOPUS See more information about DAM, M. T. on Web of Science, SO, J. See more information about  SO, J. on SCOPUS See more information about  SO, J. on SCOPUS See more information about SO, J. on Web of Science, LEE, J.-G. See more information about LEE, J.-G. on SCOPUS See more information about LEE, J.-G. on SCOPUS See more information about LEE, J.-G. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,484 KB) | Citation | Downloads: 255 | Views: 791

Author keywords
immunity, susceptibility, integrated circuit, electromagnetic compatibility, electromagnetic interference

References keywords
circuits(10), integrated(9), power(8), immunity(7), electromagnetic(7), temc(6), susceptibility(6), electro(6), compat(6), modeling(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-05-31
Volume 19, Issue 2, Year 2019, On page(s): 37 - 44
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.02005
Web of Science Accession Number: 000475806300005
SCOPUS ID: 85066298408

Abstract
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This paper characterizes the immunity of I/Os under different supply voltages for fault-tolerant circuit designs against electromagnetic interference. The direct power injection approach is used as a means to characterize the immunity of circuits. In this work, the immunity characterization has been performed under two scenarios: (1) an input buffer of a Field Programmable Gate Array (FPGA) followed by a single flip-flop, and (2) the FPGA input buffer followed by a redundancy-based fault-tolerant circuit. The experimental results show that when downscaling the supply voltage through a set of nominal values (i.e., 3.3, 2.5, 1.8, 1.5, 1.2 V), the immunity of I/Os is decreased from the highest level at 3.3 V to the lowest at 1.2 V. Particularly, the maximum difference in the immunity is about 16.8 dB at the frequency of 600 MHz. Moreover, experiments demonstrate that I/O buffers followed by the redundancy-based fault-tolerant circuit can improve the immunity of the circuit up to 4 dB below the frequency band of 400 MHz. Thus, the redundancy-based fault-tolerant circuit can support I/Os to operate reliably in the harsh environment.


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