| 1/2019 - 2 |
PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic CircuitsKIREI, B. S.   , CHEREJA, V.-I.-M. , HINTEA, S. , TOPA, M. D. |
Extra paper information in    |
| Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science |
Download PDF  (1,250 KB) | Citation | Downloads: 1,504 | Views: 2,822 |
Author keywords
logic design, software libraries, power dissipation, logic gates, CMOS integrated circuits
References keywords
power(17), circuits(10), estimation(9), design(7), cmos(7), vhdl(6), systems(5), digital(5), vlsi(4), system(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2019-02-28
Volume 19, Issue 1, Year 2019, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.01002
Web of Science Accession Number: 000459986900002
SCOPUS ID: 85064200214
Abstract
In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates. |
| References | | | Cited By |
Web of Science® Times Cited: 3 [View]
View record in Web of Science® [View]
View Related Records® [View]
Updated 2 days, 10 hours ago
SCOPUS® Times Cited: 4
View record in SCOPUS® [Free preview]
View citations in SCOPUS® [Free preview]
Updated 2 days, 10 hours ago
[1] Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging, MILIC, M., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 3, Volume 19, 2019.
Digital Object Identifier: 10.4316/AECE.2019.03009 [CrossRef] [Full text]
[2] PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL, Sandor, Kirei Botond, Farcas, Calin Adrian, Topa, Marina Dana, 2020 43rd International Conference on Telecommunications and Signal Processing (TSP), ISBN 978-1-7281-6376-5, 2020.
Digital Object Identifier: 10.1109/TSP49548.2020.9163455 [CrossRef]
[3] Power and Area Estimation of Discrete Filters in CMOS Integrated Circuits, Kirei, Botond Sandor, Farcas, Calin, Topa, Marina Dana, 2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), ISBN 978-83-62065-36-3, 2019.
Digital Object Identifier: 10.23919/SPA.2019.8936762 [CrossRef]
Updated 2 days, 10 hours ago
Disclaimer: All information displayed above was retrieved by using remote connections to respective databases. For the best user experience, we update all data by using background processes, and use caches in order to reduce the load on the servers we retrieve the information from. As we have no control on the availability of the database servers and sometimes the Internet connectivity may be affected, we do not guarantee the information is correct or complete. For the most accurate data, please always consult the database sites directly. Some external links require authentication or an institutional subscription.
Web of Science® is a registered trademark of Clarivate Analytics, Scopus® is a registered trademark of Elsevier B.V., other product names, company names, brand names, trademarks and logos are the property of their respective owners.
Copyright ©2001-2024
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
