Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 1.102
JCR 5-Year IF: 0.734
Issues per year: 4
Current issue: Feb 2021
Next issue: May 2021
Avg review time: 56 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

1,601,812 unique visits
491,104 downloads
Since November 1, 2009



No robots online now


SJR SCImago RANK

SCImago Journal & Country Rank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 21 (2021)
 
     »   Issue 1 / 2021
 
 
 Volume 20 (2020)
 
     »   Issue 4 / 2020
 
     »   Issue 3 / 2020
 
     »   Issue 2 / 2020
 
     »   Issue 1 / 2020
 
 
 Volume 19 (2019)
 
     »   Issue 4 / 2019
 
     »   Issue 3 / 2019
 
     »   Issue 2 / 2019
 
     »   Issue 1 / 2019
 
 
 Volume 18 (2018)
 
     »   Issue 4 / 2018
 
     »   Issue 3 / 2018
 
     »   Issue 2 / 2018
 
     »   Issue 1 / 2018
 
 
 Volume 17 (2017)
 
     »   Issue 4 / 2017
 
     »   Issue 3 / 2017
 
     »   Issue 2 / 2017
 
     »   Issue 1 / 2017
 
 
  View all issues  


FEATURED ARTICLE

Improved Wind Speed Prediction Using Empirical Mode Decomposition, ZHANG, Y., ZHANG, C., SUN, J., GUO, J.
Issue 2/2018

AbstractPlus






LATEST NEWS

2020-Jun-29
Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

2020-Jun-11
Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

2019-Dec-16
Starting on the 15th of December 2019 all paper authors are required to enter their SCOPUS IDs. You may use the free SCOPUS ID lookup form to find yours in case you don't remember it.

2019-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

2018-May-31
Starting today, the minimum number a pages for a paper is 8, so all submitted papers should have 8, 10 or 12 pages. No exceptions will be accepted.

Read More »


    
 

  1/2019 - 2

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

KIREI, B. S. See more information about KIREI, B. S. on SCOPUS See more information about KIREI, B. S. on IEEExplore See more information about KIREI, B. S. on Web of Science, CHEREJA, V.-I.-M. See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about CHEREJA, V.-I.-M. on Web of Science, HINTEA, S. See more information about  HINTEA, S. on SCOPUS See more information about  HINTEA, S. on SCOPUS See more information about HINTEA, S. on Web of Science, TOPA, M. D. See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,250 KB) | Citation | Downloads: 547 | Views: 1,195

Author keywords
logic design, software libraries, power dissipation, logic gates, CMOS integrated circuits

References keywords
power(17), circuits(10), estimation(9), design(7), cmos(7), vhdl(6), systems(5), digital(5), vlsi(4), system(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-02-28
Volume 19, Issue 1, Year 2019, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.01002
Web of Science Accession Number: 000459986900002
SCOPUS ID: 85064200214

Abstract
Quick view
Full text preview
In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates.


References | Cited By

Cited-By Clarivate Web of Science

Web of Science® Times Cited: 2 [View]
View record in Web of Science® [View]
View Related Records® [View]

Updated 3 days, 23 hours ago


Cited-By SCOPUS

SCOPUS® Times Cited: 4
View record in SCOPUS®
[Free preview]
View citations in SCOPUS® [Free preview]

Updated 3 days, 23 hours ago

Cited-By CrossRef

[1] Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging, MILIC, M., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 3, Volume 19, 2019.
Digital Object Identifier: 10.4316/AECE.2019.03009
[CrossRef] [Full text]

[2] PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL, Sandor, Kirei Botond, Farcas, Calin Adrian, Topa, Marina Dana, 2020 43rd International Conference on Telecommunications and Signal Processing (TSP), ISBN 978-1-7281-6376-5, 2020.
Digital Object Identifier: 10.1109/TSP49548.2020.9163455
[CrossRef]

[3] Power and Area Estimation of Discrete Filters in CMOS Integrated Circuits, Kirei, Botond Sandor, Farcas, Calin, Topa, Marina Dana, 2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), ISBN 978-83-62065-36-3, 2019.
Digital Object Identifier: 10.23919/SPA.2019.8936762
[CrossRef]

Updated 4 days ago

Disclaimer: All information displayed above was retrieved by using remote connections to respective databases. For the best user experience, we update all data by using background processes, and use caches in order to reduce the load on the servers we retrieve the information from. As we have no control on the availability of the database servers and sometimes the Internet connectivity may be affected, we do not guarantee the information is correct or complete. For the most accurate data, please always consult the database sites directly. Some external links require authentication or an institutional subscription.

Web of Science® is a registered trademark of Clarivate Analytics, Scopus® is a registered trademark of Elsevier B.V., other product names, company names, brand names, trademarks and logos are the property of their respective owners.


Copyright ©2001-2021
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: