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FACTS & FIGURES

JCR Impact Factor: 1.102
JCR 5-Year IF: 0.734
Issues per year: 4
Current issue: Feb 2021
Next issue: May 2021
Avg review time: 56 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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MOST RECENT ISSUES

 Volume 21 (2021)
 
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 Volume 17 (2017)
 
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FEATURED ARTICLE

Improved Wind Speed Prediction Using Empirical Mode Decomposition, ZHANG, Y., ZHANG, C., SUN, J., GUO, J.
Issue 2/2018

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LATEST NEWS

2020-Jun-29
Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

2020-Jun-11
Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

2019-Dec-16
Starting on the 15th of December 2019 all paper authors are required to enter their SCOPUS IDs. You may use the free SCOPUS ID lookup form to find yours in case you don't remember it.

2019-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

2018-May-31
Starting today, the minimum number a pages for a paper is 8, so all submitted papers should have 8, 10 or 12 pages. No exceptions will be accepted.

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  1/2015 - 14

 HIGHLY CITED PAPER 

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

KAZMI, M. See more information about KAZMI, M. on SCOPUS See more information about KAZMI, M. on IEEExplore See more information about KAZMI, M. on Web of Science, AZIZ, A. See more information about  AZIZ, A. on SCOPUS See more information about  AZIZ, A. on SCOPUS See more information about AZIZ, A. on Web of Science, AKHTAR, P. See more information about  AKHTAR, P. on SCOPUS See more information about  AKHTAR, P. on SCOPUS See more information about AKHTAR, P. on Web of Science, KUNDI, D.-S. See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (780 KB) | Citation | Downloads: 475 | Views: 2,967

Author keywords
buffer storage, convolver, field programmable gate array, image processing, image storage

References keywords
processing(15), fpga(13), systems(11), image(11), time(10), real(10), implementation(7), design(7), vision(6), hardware(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 95 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01014
Web of Science Accession Number: 000352158600014
SCOPUS ID: 84924812669

Abstract
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Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs) are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA) based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs) implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs) are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU). Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps). Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.


References | Cited By

Cited-By Clarivate Web of Science

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Cited-By SCOPUS

SCOPUS® Times Cited: 4
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Cited-By CrossRef

[1] Resource-Efficient Image Buffer Architecture for Neighborhood Processors, Kazmi, Majida, Aziz, Arshad, Khan, Hashim Raza, Qazi, Saad Ahmed, Stergioulas, Lampros K., IEEE Access, ISSN 2169-3536, Issue , 2020.
Digital Object Identifier: 10.1109/ACCESS.2020.3025344
[CrossRef]

[2] A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure, CHIPER, D. F., CRACAN, A., BURDIA, D., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 17, 2017.
Digital Object Identifier: 10.4316/AECE.2017.01011
[CrossRef] [Full text]

Updated 1 week, 2 days ago

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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