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FPGA Based Compact and Efficient Full Image Buffering for Neighborhood OperationsKAZMI, M. , AZIZ, A. , AKHTAR, P. , KUNDI, D.-S.
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buffer storage, convolver, field programmable gate array, image processing, image storage
processing(15), fpga(13), systems(11), image(11), time(10), real(10), implementation(7), design(7), vision(6), hardware(6)
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About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 95 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01014
Web of Science Accession Number: 000352158600014
SCOPUS ID: 84924812669
Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs) are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA) based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs) implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs) are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU). Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps). Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.
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 Resource-Efficient Image Buffer Architecture for Neighborhood Processors, Kazmi, Majida, Aziz, Arshad, Khan, Hashim Raza, Qazi, Saad Ahmed, Stergioulas, Lampros K., IEEE Access, ISSN 2169-3536, Issue , 2020.
Digital Object Identifier: 10.1109/ACCESS.2020.3025344 [CrossRef]
 A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure, CHIPER, D. F., CRACAN, A., BURDIA, D., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 17, 2017.
Digital Object Identifier: 10.4316/AECE.2017.01011 [CrossRef] [Full text]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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