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JCR Impact Factor: 1.102
JCR 5-Year IF: 0.734
Issues per year: 4
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

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  2/2010 - 9

Conceptual Implementation of Sample Rate Convertors for DACs

ANTONESEI, G. See more information about ANTONESEI, G. on SCOPUS See more information about ANTONESEI, G. on IEEExplore See more information about ANTONESEI, G. on Web of Science, TURCU, C. See more information about  TURCU, C. on SCOPUS See more information about  TURCU, C. on SCOPUS See more information about TURCU, C. on Web of Science, GRAUR, A. See more information about GRAUR, A. on SCOPUS See more information about GRAUR, A. on SCOPUS See more information about GRAUR, A. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (2,568 KB) | Citation | Downloads: 1,019 | Views: 4,004

Author keywords
DAC, CIC, mobile phone audio subsystem, multirate filtering, sample rate converter

References keywords
No relevant keywords could be extracted from the references.

About this article
Date of Publication: 2010-05-31
Volume 10, Issue 2, Year 2010, On page(s): 53 - 60
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2010.02009
Web of Science Accession Number: 000280312600009
SCOPUS ID: 77954631109

Abstract
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One of most common and difficult challenge when creating a single SoC with digital (sub)sections is caused by the various master clock (MCLK) frequencies that each individual IC had originally. There are several methods to solve this, but when constraint by price and power consumption, the design engineers must find the optimum one. The sample rate converters (SRC) are an example of solution that can simplify the architecture in some of these cases. However, even for the SRCs themselves, we need to come up with novel and efficient architectures. This paper presents such an example from mobile phones chips on how to successfully mix on the same silicon, an audio sigma-delta DAC which should support all the standard audio rates using a 13MHz MCLK frequency imposed by the RF section incorporated inside the same chip. The document will go from showing the top-level digital signal processing down to the actual hardware implementation.


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