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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  1/2017 - 5

 HIGH-IMPACT PAPER 

Efficient FPGA Implementation of High-Throughput Mixed Radix Multipath Delay Commutator FFT Processor for MIMO-OFDM

DALI, M. See more information about DALI, M. on SCOPUS See more information about DALI, M. on IEEExplore See more information about DALI, M. on Web of Science, GUESSOUM, A. See more information about  GUESSOUM, A. on SCOPUS See more information about  GUESSOUM, A. on SCOPUS See more information about GUESSOUM, A. on Web of Science, GIBSON, R. M. See more information about  GIBSON, R. M. on SCOPUS See more information about  GIBSON, R. M. on SCOPUS See more information about GIBSON, R. M. on Web of Science, AMIRA, A. See more information about  AMIRA, A. on SCOPUS See more information about  AMIRA, A. on SCOPUS See more information about AMIRA, A. on Web of Science, RAMZAN, N. See more information about RAMZAN, N. on SCOPUS See more information about RAMZAN, N. on SCOPUS See more information about RAMZAN, N. on Web of Science
 
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Download PDF pdficon (1,687 KB) | Citation | Downloads: 1,077 | Views: 3,256

Author keywords
fast fourier transform, field programmable gate arrays, mimo, ofdm, parallel architecture

References keywords
systems(18), processor(11), ofdm(10), mimo(7), circuits(7), vlsi(6), very(6), tvlsi(6), scale(6), large(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 27 - 38
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01005
Web of Science Accession Number: 000396335900005
SCOPUS ID: 85014212241

Abstract
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This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively.


References | Cited By  «-- Click to see who has cited this paper

[1] D. Gesbert, M. Shafi, D. Shiu, P.J. Smith, and A. Naguib, "From theory to practice: an overview of MIMO space-time coded wireless systems," IEEE J. Select. Areas Commun., vol. 21, no. 3, pp. 281-302, Apr 2003.
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[2] J. A. C. Bingham, "Multicarrier modulation for data transmission: an idea whose time has come," IEEE Communications Magazine, vol. 28, pp. 5-14, May 1990.
[CrossRef] [Web of Science Times Cited 1942] [SCOPUS Times Cited 2745]


[3] H. Sampath, S. Talwar, J. Tellado, V. Erceg, A. Paulraj, "A fourth generation MIMO-OFDM: broadband wireless system: Design, performance, and field trial results," Communications Magazine, IEEE, vol. 40, no. 9, pp. 143-149, Sep. 2002.
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[CrossRef] [Web of Science Times Cited 275] [SCOPUS Times Cited 366]


[5] H. Y. Chen, J. N. Lin, H. S. Hu, S. J. Jou, "STBC-OFDM downlink baseband receiver for mobile WMAN," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 21,no. 1, pp. 43-54, Jan 2013.
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[CrossRef]


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[CrossRef] [Web of Science Times Cited 55] [SCOPUS Times Cited 76]


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[CrossRef]


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[CrossRef] [SCOPUS Times Cited 20]


[19] E. E. Swartzlander, W. K. W. Young, S. J. Joseph, "A radix-4 delay commutator for fast Fourier transform processor implementation," IEEE J. of Solid-State Circuits, vol. 19, no. 5, pp. 702-709, Oct. 1984.
[CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 91]


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[CrossRef] [Web of Science Times Cited 127] [SCOPUS Times Cited 182]


[22] M. Garrido, M. Acevedo, A.. Ehliar, O. Gustafsson, "Challenging the limits of FFT performance on FPGAs," in Proc. IEEE International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2014, pp. 172-175.
[CrossRef] [SCOPUS Times Cited 29]


[23] Z. Wang, X. Liu, B. He, F. Yu, "A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 793-977, May 2015.
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[24] S. Uzun, A. Amira, A. Bouridane, "FPGA implementations of fast Fourier transforms for real-time signal and image processing," in IET Proc. in Vision, Image and Signal Processing, vol. 152, no. 3, pp. 283-296, Jun. 2005.
[CrossRef] [Web of Science Times Cited 86] [SCOPUS Times Cited 114]




References Weight

Web of Science® Citations for all references: 5,091 TCR
SCOPUS® Citations for all references: 6,930 TCR

Web of Science® Average Citations per reference: 204 ACR
SCOPUS® Average Citations per reference: 277 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-04-17 15:10 in 140 seconds.




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