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Enhanced Interrupt Response Time in the nMPRA based on Embedded Real Time MicrocontrollersGAITAN, N. C.
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architecture, operating systems, registers, scheduling, software
gaitan(14), hardware(12), systems(8), time(7), architecture(7), real(6), nmpra(6), icstcc(6), control(6), theory(5)
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About this article
Date of Publication: 2017-08-31
Volume 17, Issue 3, Year 2017, On page(s): 77 - 84
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.03010
Web of Science Accession Number: 000410369500010
SCOPUS ID: 85028523573
In any real-time operating system, task switching and scheduling, interrupts, synchronization and communication between processes, represent major problems. The implementation of these mechanisms through software generates significant delays for many applications. The nMPRA (Multi Pipeline Register Architecture) architecture is designed for the implementation of real-time embedded microcontrollers. It supports the competitive execution of n tasks, enabling very fast switching between them, with a usual delay of one machine cycle and a maximum of 3 machine cycles, for the memory-related work instructions. This is because each task has its own PC (Program Counter), set of pipeline registers and a general registers file. The nMPRA is provided with an advanced distributed interrupt controller that implements the concept of interrupts as threads. This allows the attachment of one or more interrupts to the same task. In this context, the original contribution of this article is to presents the solutions for improving the response time to interrupts when a task has attached a large number of interrupts. The proposed solutions enhance the original architecture for interrupts logic in order to transfer control, to the interrupt handler as soon as possible, and to create an interrupt prioritization at task level.
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 The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGA, CIOBANU, E.-E., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 18, 2018.
Digital Object Identifier: 10.4316/AECE.2018.01017 [CrossRef] [Full text]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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