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JCR Impact Factor: 0.650
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2019-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

2018-May-31
Starting today, the minimum number a pages for a paper is 8, so all submitted papers should have 8, 10 or 12 pages. No exceptions will be accepted.

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  1/2016 - 13

Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

NIMARA, S. See more information about NIMARA, S. on SCOPUS See more information about NIMARA, S. on IEEExplore See more information about NIMARA, S. on Web of Science, AMARICAI, A. See more information about  AMARICAI, A. on SCOPUS See more information about  AMARICAI, A. on SCOPUS See more information about AMARICAI, A. on Web of Science, BONCALO, O. See more information about  BONCALO, O. on SCOPUS See more information about  BONCALO, O. on SCOPUS See more information about BONCALO, O. on Web of Science, POPA, M. See more information about POPA, M. on SCOPUS See more information about POPA, M. on SCOPUS See more information about POPA, M. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,191 KB) | Citation | Downloads: 347 | Views: 1,544

Author keywords
digital circuits, probabilistic circuits, register transfer level, reliability, simulated fault injection

References keywords
fault(14), test(10), design(10), level(8), circuits(8), injection(7), systems(6), probabilistic(6), vlsi(5), vhdl(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 93 - 98
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01013
Web of Science Accession Number: 000376995400013
SCOPUS ID: 84960108449

Abstract
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This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit - the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.


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Copyright ©2001-2019
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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