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Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit DescriptionsNIMARA, S. , AMARICAI, A. , BONCALO, O. , POPA, M.
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digital circuits, probabilistic circuits, register transfer level, reliability, simulated fault injection
fault(14), test(10), design(10), level(8), circuits(8), injection(7), systems(6), probabilistic(6), vlsi(5), vhdl(4)
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About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 93 - 98
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01013
Web of Science Accession Number: 000376995400013
SCOPUS ID: 84960108449
This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit - the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.
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 Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing Units, Nimara, Sergiu, 2019 22nd Euromicro Conference on Digital System Design (DSD), ISBN 978-1-7281-2862-7, 2019.
Digital Object Identifier: 10.1109/DSD.2019.00096 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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