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Embedded Processor Oriented Compiler InfrastructureDJUKIC, M. , POPOVIC, M. , CETIC, N. , POVAZAN, I.
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digital signal processors, embedded software, fixed-point arithmetic, software tools
embedded(12), systems(10), compiler(10), code(10), optimization(7), design(7), compilers(6), processors(5), generation(5), sigplan(4)
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About this article
Date of Publication: 2014-08-31
Volume 14, Issue 3, Year 2014, On page(s): 123 - 130
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.03016
Web of Science Accession Number: 000340869800016
SCOPUS ID: 84907337455
In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.
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 An Automatic Instruction-Level Parallelization of Machine Code, MARINKOVIC, V., POPOVIC, M., DJUKIC, M., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 18, 2018.
Digital Object Identifier: 10.4316/AECE.2018.01004 [CrossRef] [Full text]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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