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Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule SelectionRAM, D. S. H. , BHUVANESWARI, M. C. , UMADEVI, S.
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high level synthesis, field programmable gate arrays, power dissipation, genetic algorithms, reconfigurable logic
power(11), design(10), vlsi(9), systems(8), optimization(7), level(7), high(7), integration(5), evolutionary(5), very(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 85 - 92
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04015
Web of Science Accession Number: 000331461300015
SCOPUS ID: 84890198448
FPGAs are increasingly being used to implement data path intensive algorithms for signal processing and image processing applications. In High Level Synthesis of Data Flow Graphs targeted at FPGAs, the effect of interconnect resources such as multiplexers must be considered since they contribute significantly to the area and switching power. We propose a binding framework for behavioral synthesis of Data Flow Graphs (DFGs) onto FPGA targets with power reduction as the main criterion. The technique uses a multi-objective GA, NSGA II for design space exploration to identify schedules that have the potential to yield low-power bindings from a population of non-dominated solutions. A greedy constructive binding technique reported in the literature is adapted for interconnect minimization. The binding is further subjected to a perturbation process by altering the register and multiplexer assignments. Results obtained on standard DFG benchmarks indicate that our technique yields better power aware bindings than the constructive binding approach with little or no area overhead.
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 High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices, Reyes Fernández de Bulnes, Darian, Dibene Simental, Juan Carlos, Maldonado, Yazmin, Trujillo, Leonardo, AI Communications, ISSN 1875-8452, Issue 2, Volume 30, 2017.
Digital Object Identifier: 10.3233/AIC-170727 [CrossRef]
 Design Time Temperature Reduction in Mixed Polarity Dual Reed-Muller Network: a NSGA-II Based Approach, DAS, A., PRADHAN, S. N., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 20, 2020.
Digital Object Identifier: 10.4316/AECE.2020.01013 [CrossRef] [Full text]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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