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Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded SystemsZAGAN, I. , TANASE, C. A. , GAITAN, V. G.
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pipeline processing, field programmable gate arrays, architecture, operating systems, scheduling
systems(8), architecture(7), hardware(6), gaitan(6), risc(5), time(4), processor(4), fpga(4), electronics(4), eecs(4)
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About this article
Date of Publication: 2020-02-28
Volume 20, Issue 1, Year 2020, On page(s): 63 - 70
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2020.01009
Web of Science Accession Number: 000518392600009
SCOPUS ID: 85083742572
Task context switching, unitary management of events, synchronization and communication mechanisms are significant problems for each real-time operating system. For real-time systems, another overhead factor is the processor's time to execute the routine of treating external asynchronous interrupts. The main objective of this paper is to describe, implement, and validate the preemptive scheduler module as part of the hardware accelerated real-time operating system, using the RISC-V instruction set and Verilog HDL. The new architecture contains the hardware structure used for static and dynamic scheduling of the tasks, real-time management of the events, and also defines a method used to attach interrupts to tasks. In order to accomplish this objective, it was necessary to structure CPU modules so as to ensure easy adaptation to other implementations (MIPS coprocessor, ARM or RISC-V).
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