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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2020-Jun-29
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  1/2020 - 9

Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded Systems

ZAGAN, I. See more information about ZAGAN, I. on SCOPUS See more information about ZAGAN, I. on IEEExplore See more information about ZAGAN, I. on Web of Science, TANASE, C. A. See more information about  TANASE, C. A. on SCOPUS See more information about  TANASE, C. A. on SCOPUS See more information about TANASE, C. A. on Web of Science, GAITAN, V. G. See more information about GAITAN, V. G. on SCOPUS See more information about GAITAN, V. G. on SCOPUS See more information about GAITAN, V. G. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (989 KB) | Citation | Downloads: 120 | Views: 261

Author keywords
pipeline processing, field programmable gate arrays, architecture, operating systems, scheduling

References keywords
systems(8), architecture(7), hardware(6), gaitan(6), risc(5), time(4), processor(4), fpga(4), electronics(4), eecs(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2020-02-28
Volume 20, Issue 1, Year 2020, On page(s): 63 - 70
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2020.01009
Web of Science Accession Number: 000518392600009
SCOPUS ID: 85083742572

Abstract
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Full text preview
Task context switching, unitary management of events, synchronization and communication mechanisms are significant problems for each real-time operating system. For real-time systems, another overhead factor is the processor's time to execute the routine of treating external asynchronous interrupts. The main objective of this paper is to describe, implement, and validate the preemptive scheduler module as part of the hardware accelerated real-time operating system, using the RISC-V instruction set and Verilog HDL. The new architecture contains the hardware structure used for static and dynamic scheduling of the tasks, real-time management of the events, and also defines a method used to attach interrupts to tasks. In order to accomplish this objective, it was necessary to structure CPU modules so as to ensure easy adaptation to other implementations (MIPS coprocessor, ARM or RISC-V).


References | Cited By  «-- Click to see who has cited this paper

[1] I. Zagan, V. G. Gaitan, "Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture," Electronics, vol 8, no. 2:211, 2019.
[CrossRef] [SCOPUS Times Cited 5]


[2] V. G. Gaitan, N. C. Gaitan, I. Ungurean, "CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661-1674, Sept. 2015.
[CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 19]


[3] E.-E. Ciobanu, "The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGA," Advances in Electrical and Computer Engineering, vol. 18, no. 1, pp. 137-144, 2018.
[CrossRef] [Full Text] [Web of Science Times Cited 2] [SCOPUS Times Cited 4]


[4] R. Paul, S. Shukla, "Partitioned security processor architecture on FPGA platform," IET Computers & Digital Techniques, vol. 12, no. 5, pp. 216-226, 2018.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 4]


[5] W. Wang, X. Zhang, Q. Hao, Z. Zhang, B. Xu, H. Dong, T. Xia, X. Wang, "Hardware-Enhanced Protection for the Runtime Data Security in Embedded Systems," MDPI Electronics, vol. 8, no. 1:52, 2019.
[CrossRef] [SCOPUS Times Cited 2]


[6] A. Melnyk, V. Melnyk, "Self-Configurable FPGA-Based Computer Systems," Advances in Electrical and Computer Engineering, vol. 13, no. 2, pp. 33-38, 2013.
[CrossRef] [Full Text] [Web of Science Times Cited 7] [SCOPUS Times Cited 12]


[7] S. Roman, H. Mecha, D. Mozos and J. Septien, "Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays," IET Computers & Digital Techniques, vol. 2, no. 6, pp. 401-412, November 2008.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 8]


[8] F. Kluge and J. Wolf, "System-Level Software for a Multi-Core MERASA Processor," Institute of Computer Science, University of Augsburg, Tech. Rep. 2009-17, October 2009.

[9] P. Kuacharoen, M. Shalan, V. J. Mooney III, "A Configurable Hardware Scheduler for Real-Time Systems," Proc. Engineering of Reconfigurable Systems and Algorithms, pp. 95-101, 2003. ISBN:193241505X

[10] J. Echague, I. Ripoll, A. Crespo, "Hard real-time preemptively scheduling with high context switch cost," Proceedings Seventh Euromicro Workshop on Real-Time Systems, Odense, Denmark, pp. 184-190, 1995.
[CrossRef] [SCOPUS Times Cited 10]


[11] S. Altmeyer, G. Gebhard, "WCET analysis for preemptive scheduling," 8th International Workshop on Worst-Case Execution Time WCET Analysis (WCET'08), Prague, Czech Republic, pp. 105-112, July 2008.
[CrossRef]


[12] TriCore 1, 32 bit Unified Processor Core, Volume 1, Core Architecture V 1.3 & V 1.3.1, Infineon Technologies AG, 81726 Munich, Germany, Jan. 2008, pp. 4-3 / 4-13.

[13] Intel i960 Jx Microprocessor Developer’s Manual. Intel Corporation, Order Number: 272483-002, Dec. 1997, pp. 7-1 ÷ 7-10.

[14] [Online] Available: Temporary on-line reference link removed - see the PDF document, Central processing unit with combined into a bank pipeline registers. DE 202012104250 U1. Owner Dodiu E., Gaitan, V. G.

[15] C. A. Tanase, "An approach of MPRA technique over ARM cache architecture," in 2016 International Conference on Development and Application Systems (DAS), Suceava, Romania, pp. 86-90, 2016.
[CrossRef] [SCOPUS Times Cited 5]


[16] A. Waterman, Y. Lee, R. Avizienis, H. Cook, D. Patterson, K. Asanovic, "The RISC-V instruction set," 2013 IEEE Hot Chips 25 Symposium (HCS), Stanford University, CA, USA, 2013.
[CrossRef] [SCOPUS Times Cited 4]


[17] A. Waterman, Y. Lee, D. Patterson, K. Asanovic, "The RISC-V Instruction Set Manual Volume I: User-Level ISA, Version 2.1," Technical Report UCB/EECS-2016-118, EECS Department, University of California, Berkeley, May 2016, pp. 9-23.

[18] I. Zagan, C. A. Tanase, V. G. Gaitan, "FPGA IMPLEMENTATION OF A CUSTOMIZED PROCESSOR BASED ON RISC-V ARCHITECTURE - CONCEPT AND THEORY OF OPERATION," Proceedings of 148th IASTEM International Conference, Rome, Italy, 2018, pp. 24-29.

[19] Y. Lee et al., "An Agile Approach to Building RISC-V Microprocessors," IEEE Micro, vol. 36, no. 2, pp. 8-20, 2016.
[CrossRef] [SCOPUS Times Cited 29]


[20] E. E Moisuc, A. B. Larionescu, V. G. Gaitan, "Hardware Event Treating in nMPRA," in 12rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 66-69, 15-17 May, 2014.
[CrossRef] [SCOPUS Times Cited 9]


[21] S. Kelinman and J. Eykholt, "Interrupts as threads," ACM SIGOPS Operating Syst. Rev., vol. 29, no. 2, pp. 21-26, Apr. 1995.
[CrossRef]


[22] A. Waterman, Y. Lee, D. Patterson, K. Asanovic, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7," Technical Report UCB/EECS-2015-49, EECS Department, University of California, Berkeley, May 2015, pp. 7-13.



References Weight

Web of Science® Citations for all references: 39 TCR
SCOPUS® Citations for all references: 111 TCR

Web of Science® Average Citations per reference: 2 ACR
SCOPUS® Average Citations per reference: 5 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2020-08-05 21:24 in 99 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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