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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2019-Jun-20
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  3/2019 - 9

Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging

MILIC, M. See more information about MILIC, M. on SCOPUS See more information about MILIC, M. on IEEExplore See more information about MILIC, M. on Web of Science
 
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Download PDF pdficon (322 KB) | Citation | Downloads: 61 | Views: 135

Author keywords
accelerated aging, circuit simulation, integrated circuit modeling, integrated circuit reliability, very large integration

References keywords
reliability(12), aging(10), design(9), analysis(8), timing(7), circuits(7), statistical(5), microelectronics(5), jmicrorel(5), vlsi(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-08-31
Volume 19, Issue 3, Year 2019, On page(s): 75 - 82
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.03009
Web of Science Accession Number: 000486574100009
SCOPUS ID: 85072177529

Abstract
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The importance of aging effects analysis in VLSI circuits increases with nowadays fast scaling of integrated circuits manufacturing technologies. Delays along paths in a digital circuit are crucial parameters that define the circuit working frequency. They degrade over time resulting in delay faults and circuit failures. The prediction of circuit long-term behavior is useful mechanism for ensuring a VLSI's lifetime reliability. In particular, paths in a digital circuit that have the largest delays are the most sensitive to gates' delay fluctuations, and consequently aging. Delay of those paths can be obtained using either aging sensors or through statistical analysis of accelerated aging experiments, but such approaches can be very difficult, time consuming and expensive for implementation. This paper suggests a new methodology capable to estimate the aging effect to digital circuit delays along multiple paths, simultaneously. The proposed technique has been developed for circuits described at a gate level, and implemented within a standard logic simulator, which enables aging analysis in initial phases of system design process. Results show that proposed methodology can efficiently estimate the long-term timing behavior of the digital circuit in a very early design stages with a small computational effort, helping the designer in selection of most reliable design choices.


References | Cited By  «-- Click to see who has cited this paper

[1] W. Wenping, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, and Y. Cao, "Statistical prediction of circuit aging under process variations," in Proc. IEEE Custom Int. Circ. Conf. 2008. pp. 13-16.
[CrossRef]


[2] S. Duan, B. Halak, and M. Zwolinski, "An ageing-aware digital synthesis approach," In 14th IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, pp. 1-4.
[CrossRef]


[3] H. M. Abbas, M. Zwolinski, and B. Halak, "Static aging analysis using 3-dimensional delay library," In ERMAVSS@DATE, 2016, pp. 34-37. [Online] Available: Temporary on-line reference link removed - see the PDF document

[4] P. F. Butzen, V. D. Bem, A. I. Reis, and R. P. Ribas, "Design of CMOS logic gates with enhanced robustness against aging degradation," Microelectronics Reliability, vol. 52, no. 9-10, 2012, pp. 1822-1826.
[CrossRef] [Web of Science Times Cited 9]


[5] S. Karapetyan, and U. Schlichtmann, "Integrating aging aware timing analysis into a commercial STA tool," In VLSI Design, Automation and Test (VLSI-DAT), April 2015. pp. 1-4. IEEE.
[CrossRef]


[6] A. Hussam, B. Khaleghi, A. Gerstlauer, and J. Henkel, "Reliability-aware design to suppress aging," In 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, pp. 1-6.
[CrossRef] [Web of Science Times Cited 6]


[7] C. Bestory, F. Marcand, and H. Levi, "Statistical analysis during the reliability simulation," Microelectronics Reliability, vol. 47, no. 9-11, 2007, pp.1353-1357,
[CrossRef] [Web of Science Times Cited 15]


[8] S. Shaheen, G. Golan, M. Azoulay, and J. Bernstein, "A comparative study of reliability for FINFET," Facta Unversitatis Series: Electronics and Energetics, vol. 31, no 3, September 2018, pp. 343-366.
[CrossRef] [Web of Science Times Cited 1]


[9] B. Li, M. Hashimoto, and U. Schlichtmann, "From process variations to reliability: A survey of timing of digital circuits in the nanometer era," IPSJ Transactions on System LSI Design Methodology, vol. 11, 2018, pp.2-15.
[CrossRef]


[10] N. Koppaetzky, M. Metzdorf, R. Eilers, D. Helms, and W. Nebel, "RT level timing modeling for aging prediction," In Proc. of the Conf. on Design, Automation & Test in Europe, March 2016, pp. 297-300, EDA Consortium.

[11] M. Milic, M. Ljubenovic, S. Dosic, and D. Lukac, "Aging aware HDL modelling of delays in logic gates," In Proc. of IcETRAN, Palic, Serbia, June 2018, pp. 896-900.

[12] D. Lorenz, M. Barke, and U Schlichtmann, "Efficiently analyzing the impact of aging effects on large integrated circuits," Microelectronics Reliability, vol. 52, no. 8, 2012, pp.1546-1552.
[CrossRef] [Web of Science Times Cited 17]


[13] J. Chen, S. Wang, N. Bidokhti, and M. Tehranipoor, "A framework for fast and accurate critical-reliability paths identification," In IEEE North Atlantic test workshop (NATW), May 2011, pp. 1-4.

[14] J. Keane, and H. K. Chris, "An odomoeter for CPUs," IEEE Spectrum, vol. 48, no. 5, 2011, pp. 28-33.
[CrossRef] [Web of Science Times Cited 13]


[15] D. Lorenz, M. Barke, and U. Schlichtmann, "Aging analysis at gate and macro cell level," In Proc. of the Int. Conf. on Computer-Aided Design, November 2010, pp. 77-84.

[16] J. H. Stathis, S. Mahapatra, and T. Grasser, "Controversial issues in negative bias temperature instability," Microelectronics Reliability, vol. 81, 2018, pp.244-251.
[CrossRef] [Web of Science Times Cited 16]


[17] A. W. Strong, E. Y. Wu, R.-P. Vollertsen, J. Sune, G. La Rosa, S. E. Rauch, and T. D. Sullivan, Reliability Wearout Mechanisms in Advanced CMOS Technologies. Series on Microelectronic Systems. IEEE Press, 2009, pp.566.

[18] E. Mizan, Efficient fault tolerance for pipelined structures and its application to superscalar and dataflow machines. Ph.D. thesis, Electrical and Computer Engineering Dept., University of Texas, Austin, 2008.

[19] K. Naghmeh, J.-L. Danger, F. Lozac'h. and S. Guilley, "Predictive aging of reliability of two delay PUFs." In International Conference on Security, Privacy, and Applied Cryptography Engineering Cham, 2016, pp. 213-232.
[CrossRef]


[20] L. Zhang, W. Chen, Y. Hu, C.C. Chen, "Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model," IEEE Trans. on CAD Integr. Circuits Syst. vol. 25, no. 6, 2006, pp:1183-1191.
[CrossRef] [Web of Science Times Cited 24]


[21] M. Sokolovic, V. Litovski, and M. Zwolinski, "New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits," Microelectronics Reliability, vol. 49, no. 2, 2009, pp.186-198.
[CrossRef] [Web of Science Times Cited 2]


[22] R. Spence, and R. Soin R, Tolerance design of electronic circuits, Addison-Wesley, 1988.

[23] D. M. Maksimovic, and V. B. Litovski, "Tuning logic simulators for timing analysis," Electronics Letters, vol. 35, no. 10, 1999, pp.800-802,
[CrossRef] [Web of Science Times Cited 8]


[24] M. Sokolovic, V. Litovski, and M. Zwolinski, "Efficient and realistic statistical worst-case delay computation using VHDL," Electrical Engineering, vol. 91, no. 4-5, 2009, pp.197.
[CrossRef] [Web of Science Times Cited 1]


[25] B. S. Kirei, V. J. M. Chereja, S. Hintea, and M. D. Topa, "PAELib: A VHDL library for area and power dissipation estimation of CMOS logic circuits," Advances in Electrical and Computer Engineering, vol. 19. no. 1, 2019, pp. 9-16.
[CrossRef] [Full Text] [Web of Science Times Cited 1]


[26] A. Agarwal, V. Zolotov, and D. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE Trans. CAD Integr. Circuits Syst., vol. 22, no. 9, 2003, pp. 1243-1260.
[CrossRef] [Web of Science Times Cited 71]




References Weight

Web of Science® Citations for all references: 184 TCR
SCOPUS® Citations for all references: 0

Web of Science® Average Citations per reference: 7 ACR
SCOPUS® Average Citations per reference: 0

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2019-10-14 07:26 in 124 seconds.




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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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