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Tuning Logic Simulator for Estimation of VLSI Timing Degradation under AgingMILIC, M.
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accelerated aging, circuit simulation, integrated circuit modeling, integrated circuit reliability, very large integration
reliability(12), aging(10), design(9), analysis(8), timing(7), circuits(7), statistical(5), microelectronics(5), jmicrorel(5), vlsi(4)
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About this article
Date of Publication: 2019-08-31
Volume 19, Issue 3, Year 2019, On page(s): 75 - 82
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.03009
Web of Science Accession Number: 000486574100009
SCOPUS ID: 85072177529
The importance of aging effects analysis in VLSI circuits increases with nowadays fast scaling of integrated circuits manufacturing technologies. Delays along paths in a digital circuit are crucial parameters that define the circuit working frequency. They degrade over time resulting in delay faults and circuit failures. The prediction of circuit long-term behavior is useful mechanism for ensuring a VLSI's lifetime reliability. In particular, paths in a digital circuit that have the largest delays are the most sensitive to gates' delay fluctuations, and consequently aging. Delay of those paths can be obtained using either aging sensors or through statistical analysis of accelerated aging experiments, but such approaches can be very difficult, time consuming and expensive for implementation. This paper suggests a new methodology capable to estimate the aging effect to digital circuit delays along multiple paths, simultaneously. The proposed technique has been developed for circuits described at a gate level, and implemented within a standard logic simulator, which enables aging analysis in initial phases of system design process. Results show that proposed methodology can efficiently estimate the long-term timing behavior of the digital circuit in a very early design stages with a small computational effort, helping the designer in selection of most reliable design choices.
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Stefan cel Mare University of Suceava, Romania
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