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High-Level Crosstalk Model in N-Coupled Through-Silicon Vias (TSVs)LEE, H. , PARK, J. K. , KIM, J. T.
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integrated circuit reliability, SPICE, crosstalk, interconnect, through-silicon via
design(13), systems(7), silicon(6), integration(6), integrated(6), circuits(6), chip(6), vias(5), technology(5), modeling(5)
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About this article
Date of Publication: 2018-08-31
Volume 18, Issue 3, Year 2018, On page(s): 9 - 14
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.03002
Web of Science Accession Number: 000442420900002
SCOPUS ID: 85052155428
This paper proposes a regression noise model that can cover the noise effect from N-coupled TSVs based on SPICE simulation and reliability analysis flow for high-level simulation using a regression model. Regression analysis is adopted to develop a simple noise model with a single parameter and use the superposition theorem to extend the number of TSV lines that produce the noise. The proposed regression model has over 99 percent accuracy with SPICE in the given parameter range. For the N-coupled TSV wire, the regression noise model has over 96 percent accuracy. This paper choose the transaction level simulation for the high-level proposed analysis flow to calculate the single bit error rate of over 100 billion transaction data in a few minutes. Our simulation result shows the effect of the N-coupled TSV crosstalk glitch noise on the single bit error rate when the probability function type of the manufacturing noise is considered.
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