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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  3/2018 - 2

High-Level Crosstalk Model in N-Coupled Through-Silicon Vias (TSVs)

LEE, H. See more information about LEE, H. on SCOPUS See more information about LEE, H. on IEEExplore See more information about LEE, H. on Web of Science, PARK, J. K. See more information about  PARK, J. K. on SCOPUS See more information about  PARK, J. K. on SCOPUS See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,593 KB) | Citation | Downloads: 411 | Views: 1,115

Author keywords
integrated circuit reliability, SPICE, crosstalk, interconnect, through-silicon via

References keywords
design(13), systems(7), silicon(6), integration(6), integrated(6), circuits(6), chip(6), vias(5), technology(5), modeling(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-08-31
Volume 18, Issue 3, Year 2018, On page(s): 9 - 14
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.03002
Web of Science Accession Number: 000442420900002
SCOPUS ID: 85052155428

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This paper proposes a regression noise model that can cover the noise effect from N-coupled TSVs based on SPICE simulation and reliability analysis flow for high-level simulation using a regression model. Regression analysis is adopted to develop a simple noise model with a single parameter and use the superposition theorem to extend the number of TSV lines that produce the noise. The proposed regression model has over 99 percent accuracy with SPICE in the given parameter range. For the N-coupled TSV wire, the regression noise model has over 96 percent accuracy. This paper choose the transaction level simulation for the high-level proposed analysis flow to calculate the single bit error rate of over 100 billion transaction data in a few minutes. Our simulation result shows the effect of the N-coupled TSV crosstalk glitch noise on the single bit error rate when the probability function type of the manufacturing noise is considered.

References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [Web of Science Times Cited 562]

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[4] Polka, Lesley Anne, et al, "Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing," Intel Technology Journal, vol. 11, no. 3, 2007.

[5] R. Weerasekera, et al, "On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits," Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, pp. 1325-1328, 2010.

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[CrossRef] [Web of Science Times Cited 674]

[7] Z. Xu, A. Beece, et al, "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network," 3D Systems Integration Conference (3DIC), 2010 IEEE International. IEEE, pp. 1-8, 2010.

[8] S. K. Lim, "Design for high performance, low power, and reliable 3D integrated circuits," Springer Science & Business Media, 2013.

[9] J. Q. Lu, "3-D Hyperintegration and Packaging Technologies for MicroNano Systems," Proceeding of IEEE, Vol. 97, no. 1, pp. 18-30, Jan. 2009.
[CrossRef] [Web of Science Times Cited 225]

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[CrossRef] [Web of Science Times Cited 386]

[11] Q. Wu, K. Rose, J. Q. Lu, T. Zhang, "Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems," IEEE International 3D System Integration Conference, San Francisco, CA, 2009.

[12] K. C. Saraswat, F. Mohammadi, "Effect of Interconnection Scaling on Time Delay of VLSI circuits," IEEE Trans. Electron Devices, Vol. 29, pp. 645-50, 1982.

[13] T. Song, et al, "Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs," Quality Electronic Design (ISQED), 2011 12th International Symposium on. IEEE, pp. 1-7, 2011.

[14] L.Cadix, et al, "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs," Interconnect Technology Conference (IITC), 2010 International. IEEE, pp. 1-3, 2010.

[15] I. Savidis, Eby G. Friedman, "Closed-form expressions of 3-D via resistance, inductance, and capacitance," IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1873-1881, 2009.
[CrossRef] [Web of Science Times Cited 119]

[16] R.Weerasekera, M. Grange, et al, "Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits." IEEE International Conference on 3D System Integration. pp. 1-8, 2009.

[17] Z. Qiaosha, et al, "3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code," Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 762-767, 2014.

[18] C. Liu, et al, "Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC," Proceedings of the 48th Design Automation Conference, pp. 783-788, 2011.

[19] K. Yoon, et al, "Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer," Electronics Packaging Technology Conference, EPTC'09. 11th, pp. 702-706, 2009.
[CrossRef] [Web of Science Times Cited 37]

[20] A. E. Engin, S. R. Narasimhan, "Modeling of crosstalk in through silicon vias," IEEE Transactions on Electromagnetic Compatibility, vol. 55, no.1, pp. 149-158, 2013.
[CrossRef] [Web of Science Times Cited 65]

[21] D. Khalil, et al, "Analytical model for the propagation delay of through silicon vias" Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, pp. 553-556, 2008.

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[23] K. Agarwal, et al, "Statistical interconnect metrics for physical-design optimization" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1273-1288, 2006.

[24] J. Moreno, et al, "Low voltage testing for interconnect opens under process variations," Test Workshop (LATW), 2012 13th Latin American. IEEE, pp. 1-6, 2012.

References Weight

Web of Science® Citations for all references: 2,068 TCR
SCOPUS® Citations for all references: 0

Web of Science® Average Citations per reference: 83 ACR
SCOPUS® Average Citations per reference: 0

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2020-09-29 02:51 in 159 seconds.

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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

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