Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 0.699
JCR 5-Year IF: 0.674
Issues per year: 4
Current issue: May 2019
Next issue: Aug 2019
Avg review time: 82 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

2,256,780 unique visits
592,486 downloads
Since November 1, 2009



No robots online now


SJR SCImago RANK

SCImago Journal & Country Rank


SEARCH ENGINES

aece.ro - Google Pagerank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 19 (2019)
 
     »   Issue 2 / 2019
 
     »   Issue 1 / 2019
 
 
 Volume 18 (2018)
 
     »   Issue 4 / 2018
 
     »   Issue 3 / 2018
 
     »   Issue 2 / 2018
 
     »   Issue 1 / 2018
 
 
 Volume 17 (2017)
 
     »   Issue 4 / 2017
 
     »   Issue 3 / 2017
 
     »   Issue 2 / 2017
 
     »   Issue 1 / 2017
 
 
 Volume 16 (2016)
 
     »   Issue 4 / 2016
 
     »   Issue 3 / 2016
 
     »   Issue 2 / 2016
 
     »   Issue 1 / 2016
 
 
  View all issues  








LATEST NEWS

2018-May-31
Starting today, the minimum number a pages for a paper is 8, so all submitted papers should have 8, 10 or 12 pages. No exceptions will be accepted.

2018-Jun-27
Clarivate Analytics published the InCites Journal Citations Report for 2017. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.699, and the JCR 5-Year Impact Factor is 0.674.

2017-Apr-04
We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

2017-Jan-30
We have the confirmation Advances in Electrical and Computer Engineering will be included in the Gale database.

Read More »


    
 

  3/2018 - 2

High-Level Crosstalk Model in N-Coupled Through-Silicon Vias (TSVs)

LEE, H. See more information about LEE, H. on SCOPUS See more information about LEE, H. on IEEExplore See more information about LEE, H. on Web of Science, PARK, J. K. See more information about  PARK, J. K. on SCOPUS See more information about  PARK, J. K. on SCOPUS See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,593 KB) | Citation | Downloads: 304 | Views: 478

Author keywords
integrated circuit reliability, SPICE, crosstalk, interconnect, through-silicon via

References keywords
design(13), systems(7), silicon(6), integration(6), integrated(6), circuits(6), chip(6), vias(5), technology(5), modeling(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-08-31
Volume 18, Issue 3, Year 2018, On page(s): 9 - 14
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.03002
Web of Science Accession Number: 000442420900002
SCOPUS ID: 85052155428

Abstract
Quick view
Full text preview
This paper proposes a regression noise model that can cover the noise effect from N-coupled TSVs based on SPICE simulation and reliability analysis flow for high-level simulation using a regression model. Regression analysis is adopted to develop a simple noise model with a single parameter and use the superposition theorem to extend the number of TSV lines that produce the noise. The proposed regression model has over 99 percent accuracy with SPICE in the given parameter range. For the N-coupled TSV wire, the regression noise model has over 96 percent accuracy. This paper choose the transaction level simulation for the high-level proposed analysis flow to calculate the single bit error rate of over 100 billion transaction data in a few minutes. Our simulation result shows the effect of the N-coupled TSV crosstalk glitch noise on the single bit error rate when the probability function type of the manufacturing noise is considered.


References | Cited By  «-- Click to see who has cited this paper

[1] S. Borkar, "Design challenges of technology scaling," IEEE micro, vol. 19, no. 4 pp. 23-29, 1999.
[CrossRef] [Web of Science Times Cited 515] [SCOPUS Times Cited 724]


[2] M. Swaminathan, et al, "Power integrity modeling and design for semiconductors and systems," Pearson Education, 2007.
[CrossRef]


[3] Y. Zhang, et al, "Prediction and comparison of high-performance on-chip global interconnection," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, pp. 1154-1166, 2011.
[CrossRef] [SCOPUS Times Cited 6]


[4] Polka, Lesley Anne, et al, "Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing," Intel Technology Journal, vol. 11, no. 3, 2007.
[CrossRef]


[5] R. Weerasekera, et al, "On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits," Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, pp. 1325-1328, 2010.
[CrossRef]


[6] K. Banerjee, et al, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE, vol. 89, no. 5, pp. 602-633, 2001.
[CrossRef] [Web of Science Times Cited 644] [SCOPUS Times Cited 749]


[7] Z. Xu, A. Beece, et al, "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network," 3D Systems Integration Conference (3DIC), 2010 IEEE International. IEEE, pp. 1-8, 2010.
[CrossRef] [SCOPUS Times Cited 30]


[8] S. K. Lim, "Design for high performance, low power, and reliable 3D integrated circuits," Springer Science & Business Media, 2013.
[CrossRef] [SCOPUS Times Cited 17]


[9] J. Q. Lu, "3-D Hyperintegration and Packaging Technologies for MicroNano Systems," Proceeding of IEEE, Vol. 97, no. 1, pp. 18-30, Jan. 2009.
[CrossRef] [Web of Science Times Cited 206] [SCOPUS Times Cited 238]


[10] R. S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", Proceedings of IEEE, vol. 94, no. 6, pp. 1214-1224, June 2006.
[CrossRef] [Web of Science Times Cited 349] [SCOPUS Times Cited 431]


[11] Q. Wu, K. Rose, J. Q. Lu, T. Zhang, "Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems," IEEE International 3D System Integration Conference, San Francisco, CA, 2009.
[CrossRef] [SCOPUS Times Cited 17]


[12] K. C. Saraswat, F. Mohammadi, "Effect of Interconnection Scaling on Time Delay of VLSI circuits," IEEE Trans. Electron Devices, Vol. 29, pp. 645-50, 1982.
[CrossRef] [SCOPUS Times Cited 65]


[13] T. Song, et al, "Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs," Quality Electronic Design (ISQED), 2011 12th International Symposium on. IEEE, pp. 1-7, 2011.
[CrossRef] [SCOPUS Times Cited 29]


[14] L.Cadix, et al, "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs," Interconnect Technology Conference (IITC), 2010 International. IEEE, pp. 1-3, 2010.
[CrossRef] [SCOPUS Times Cited 19]


[15] I. Savidis, Eby G. Friedman, "Closed-form expressions of 3-D via resistance, inductance, and capacitance," IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1873-1881, 2009.
[CrossRef] [Web of Science Times Cited 110] [SCOPUS Times Cited 160]


[16] R.Weerasekera, M. Grange, et al, "Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits." IEEE International Conference on 3D System Integration. pp. 1-8, 2009.
[CrossRef] [SCOPUS Times Cited 77]


[17] Z. Qiaosha, et al, "3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code," Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 762-767, 2014.
[CrossRef] [SCOPUS Times Cited 21]


[18] C. Liu, et al, "Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC," Proceedings of the 48th Design Automation Conference, pp. 783-788, 2011.
[CrossRef]


[19] K. Yoon, et al, "Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer," Electronics Packaging Technology Conference, EPTC'09. 11th, pp. 702-706, 2009.
[CrossRef] [Web of Science Times Cited 25] [SCOPUS Times Cited 51]


[20] A. E. Engin, S. R. Narasimhan, "Modeling of crosstalk in through silicon vias," IEEE Transactions on Electromagnetic Compatibility, vol. 55, no.1, pp. 149-158, 2013.
[CrossRef] [Web of Science Times Cited 58] [SCOPUS Times Cited 68]


[21] D. Khalil, et al, "Analytical model for the propagation delay of through silicon vias" Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, pp. 553-556, 2008.
[CrossRef] [SCOPUS Times Cited 35]


[22] Y. Eo, et al, "A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design," IEEE transactions on Electron Devices, vol. 47, no. 1, pp. 129-140, 2000.
[CrossRef] [SCOPUS Times Cited 39]


[23] K. Agarwal, et al, "Statistical interconnect metrics for physical-design optimization" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1273-1288, 2006.
[CrossRef] [Web of Science Times Cited 95] [SCOPUS Times Cited 42]


[24] J. Moreno, et al, "Low voltage testing for interconnect opens under process variations," Test Workshop (LATW), 2012 13th Latin American. IEEE, pp. 1-6, 2012.
[CrossRef] [SCOPUS Times Cited 2]




References Weight

Web of Science® Citations for all references: 2,002 TCR
SCOPUS® Citations for all references: 2,820 TCR

Web of Science® Average Citations per reference: 80 ACR
SCOPUS® Average Citations per reference: 113 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2019-06-16 15:59 in 164 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2019
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: