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High-Level Crosstalk Model in N-Coupled Through-Silicon Vias (TSVs)LEE, H. , PARK, J. K. , KIM, J. T.
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integrated circuit reliability, SPICE, crosstalk, interconnect, through-silicon via
design(13), systems(7), silicon(6), integration(6), integrated(6), circuits(6), chip(6), vias(5), technology(5), modeling(5)
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About this article
Date of Publication: 2018-08-31
Volume 18, Issue 3, Year 2018, On page(s): 9 - 14
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.03002
Web of Science Accession Number: 000442420900002
SCOPUS ID: 85052155428
This paper proposes a regression noise model that can cover the noise effect from N-coupled TSVs based on SPICE simulation and reliability analysis flow for high-level simulation using a regression model. Regression analysis is adopted to develop a simple noise model with a single parameter and use the superposition theorem to extend the number of TSV lines that produce the noise. The proposed regression model has over 99 percent accuracy with SPICE in the given parameter range. For the N-coupled TSV wire, the regression noise model has over 96 percent accuracy. This paper choose the transaction level simulation for the high-level proposed analysis flow to calculate the single bit error rate of over 100 billion transaction data in a few minutes. Our simulation result shows the effect of the N-coupled TSV crosstalk glitch noise on the single bit error rate when the probability function type of the manufacturing noise is considered.
|References|||||Cited By «-- Click to see who has cited this paper|
| S. Borkar, "Design challenges of technology scaling," IEEE micro, vol. 19, no. 4 pp. 23-29, 1999. |
[CrossRef] [Web of Science Times Cited 562]
 M. Swaminathan, et al, "Power integrity modeling and design for semiconductors and systems," Pearson Education, 2007.
 Y. Zhang, et al, "Prediction and comparison of high-performance on-chip global interconnection," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, pp. 1154-1166, 2011.
 Polka, Lesley Anne, et al, "Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing," Intel Technology Journal, vol. 11, no. 3, 2007.
 R. Weerasekera, et al, "On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits," Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, pp. 1325-1328, 2010.
 K. Banerjee, et al, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE, vol. 89, no. 5, pp. 602-633, 2001.
[CrossRef] [Web of Science Times Cited 674]
 Z. Xu, A. Beece, et al, "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network," 3D Systems Integration Conference (3DIC), 2010 IEEE International. IEEE, pp. 1-8, 2010.
 S. K. Lim, "Design for high performance, low power, and reliable 3D integrated circuits," Springer Science & Business Media, 2013.
 J. Q. Lu, "3-D Hyperintegration and Packaging Technologies for MicroNano Systems," Proceeding of IEEE, Vol. 97, no. 1, pp. 18-30, Jan. 2009.
[CrossRef] [Web of Science Times Cited 225]
 R. S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", Proceedings of IEEE, vol. 94, no. 6, pp. 1214-1224, June 2006.
[CrossRef] [Web of Science Times Cited 386]
 Q. Wu, K. Rose, J. Q. Lu, T. Zhang, "Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems," IEEE International 3D System Integration Conference, San Francisco, CA, 2009.
 K. C. Saraswat, F. Mohammadi, "Effect of Interconnection Scaling on Time Delay of VLSI circuits," IEEE Trans. Electron Devices, Vol. 29, pp. 645-50, 1982.
 T. Song, et al, "Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs," Quality Electronic Design (ISQED), 2011 12th International Symposium on. IEEE, pp. 1-7, 2011.
 L.Cadix, et al, "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs," Interconnect Technology Conference (IITC), 2010 International. IEEE, pp. 1-3, 2010.
 I. Savidis, Eby G. Friedman, "Closed-form expressions of 3-D via resistance, inductance, and capacitance," IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1873-1881, 2009.
[CrossRef] [Web of Science Times Cited 119]
 R.Weerasekera, M. Grange, et al, "Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits." IEEE International Conference on 3D System Integration. pp. 1-8, 2009.
 Z. Qiaosha, et al, "3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code," Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 762-767, 2014.
 C. Liu, et al, "Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC," Proceedings of the 48th Design Automation Conference, pp. 783-788, 2011.
 K. Yoon, et al, "Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer," Electronics Packaging Technology Conference, EPTC'09. 11th, pp. 702-706, 2009.
[CrossRef] [Web of Science Times Cited 37]
 A. E. Engin, S. R. Narasimhan, "Modeling of crosstalk in through silicon vias," IEEE Transactions on Electromagnetic Compatibility, vol. 55, no.1, pp. 149-158, 2013.
[CrossRef] [Web of Science Times Cited 65]
 D. Khalil, et al, "Analytical model for the propagation delay of through silicon vias" Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, pp. 553-556, 2008.
 Y. Eo, et al, "A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design," IEEE transactions on Electron Devices, vol. 47, no. 1, pp. 129-140, 2000.
 K. Agarwal, et al, "Statistical interconnect metrics for physical-design optimization" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1273-1288, 2006.
 J. Moreno, et al, "Low voltage testing for interconnect opens under process variations," Test Workshop (LATW), 2012 13th Latin American. IEEE, pp. 1-6, 2012.
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