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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
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Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2019-Jun-20
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  2/2018 - 8

Expansible Network-on-Chip Architecture

PIRES, I. L. P. See more information about PIRES, I. L. P. on SCOPUS See more information about PIRES, I. L. P. on IEEExplore See more information about PIRES, I. L. P. on Web of Science, ALVES, M. A. Z. See more information about  ALVES, M. A. Z. on SCOPUS See more information about  ALVES, M. A. Z. on SCOPUS See more information about ALVES, M. A. Z. on Web of Science, ALBINI, L. C. P. See more information about ALBINI, L. C. P. on SCOPUS See more information about ALBINI, L. C. P. on SCOPUS See more information about ALBINI, L. C. P. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,341 KB) | Citation | Downloads: 200 | Views: 658

Author keywords
computer architecture, multiprocessor interconnection, system-on-chip, reconfigurable architectures, wireless networks

References keywords
chip(11), parallel(9), network(8), architecture(6), systems(5), performance(5), circuits(5), specification(4), multi(4), isscc(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-05-31
Volume 18, Issue 2, Year 2018, On page(s): 61 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.02008
Web of Science Accession Number: 000434245000008
SCOPUS ID: 85047879531

Abstract
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Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the processing elements. However, the communication outside the chip commonly uses high performance links which have the entire communication protocol stack overhead. This paper introduces the Expansible NoC concept and architecture, which is formed by wired and wireless NoC components in order to provide a low overhead interconnection for intra-chip and inter-chip communication. ENoC couples both networks with the same simplified protocol, enabling the transmission of parallel messages directly in the NoC level. The ability of identifying new communicant on-the-fly increases its flexibility, expanding the system boundaries every time a new system is connected. The ENoC inter-chip wireless link reaches short distances working at 60 GHz with Orthogonal Frequency Division Multiplexing with Quadrature Amplitude Modulation, enabling high bandwidth communication for systems inside a single cluster rack. Experimental evaluations were performed using the Noxim simulator executing computational fluid dynamics benchmark applications. Results show that the proposed architecture improves up to 38% the performance when compared to the newest related work.


References | Cited By  «-- Click to see who has cited this paper

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References Weight

Web of Science® Citations for all references: 1,910 TCR
SCOPUS® Citations for all references: 4,702 TCR

Web of Science® Average Citations per reference: 64 ACR
SCOPUS® Average Citations per reference: 157 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2019-10-15 11:17 in 136 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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