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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

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  1/2018 - 17

The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGA

CIOBANU, E.-E. See more information about CIOBANU, E.-E. on SCOPUS See more information about CIOBANU, E.-E. on IEEExplore See more information about CIOBANU, E.-E. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (2,468 KB) | Citation | Downloads: 90 | Views: 190

Author keywords
architecture, operating systems, pipeline registers, interrupts, hardware scheduler

References keywords
gaitan(11), hardware(9), architecture(9), nmpra(6), time(5), systems(5), system(5), research(5), implementation(5), technology(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-02-28
Volume 18, Issue 1, Year 2018, On page(s): 137 - 144
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.01017
SCOPUS ID: 85043233566

Abstract
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Full text preview
The MPRA (Multi Pipeline Register Architecture) was modified and converted into n-task MPRA (nMPRA) by replicating the pipeline registers. While the original MPRA provided hardware scheduling, the interrupts and the events caused too long delays. The author proposes the original solutions for the interrupts and the events treatment, which represent the author's contribution to improving nMPRA; after the theoretical presentations of these solutions in the author's previous articles, this paper presents the implementations of the schemes, the results of the tests and the improved schemes. The MPRA, MPRA4 and MPRA8 implementations on FPGA (Field Programmable Gate Array) were used to evaluate performances. A detailed analysis, partially presented in this paper, shows other advantages: no extra software is required, the hardware implementation is simple, the interrupts and events are similarly handled and the tasks synchronizations and communications are completely based on hardware; MPRA has a low power consumption, even multiplied by eight times, it is reasonably necessary memory and logic resource consumption multiplied by about four times at MPRA4 (compared to MPRA) and by about eight times at MPRA8.


References | Cited By  «-- Click to see who has cited this paper

[1] V. G. Gaitan, N. C. Gaitan, I. Ungurean, "CPU architecture based on a hardware scheduler and independent pipeline registers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 23, Issue: 9, September 2015, ISSN: 1063-8210, pp.: 1661-1674.
[CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 8]


[2] I. Zagan, V. G. Gaitan, "Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy", Advances in Electrical and Computer Engineering, vol. 16, no. 4, pp. 45-50, 2016,
[CrossRef] [Full Text] [Web of Science Times Cited 4] [SCOPUS Times Cited 3]


[3] N. C. Gaitan, "Enhanced Interrupt Response Time in the nMPRA based on Embedded Real Time Microcontrollers", Advances in Electrical and Computer Engineering, vol.17, no. 3, pp. 77-84, 2017,
[CrossRef] [Full Text] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]


[4] I. Zagan, V. G. Gaitan, "Implementation of nMPRA CPU Architecture based on Preemptive Hardware Scheduler Engine and Different Scheduling Algorithms", IET Computers & Digital Techniques, vol. 11, issue 6, november 2017, p. 221-230,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]


[5] K. M. Mallachiev, N. V. Pakulin, A.V. Khoroshilov, "Design and architecture of real-time operating system", Trudy ISP RAN/Proc. ISP RAS, vol. 28, issue 2, 2016, pp. 181- 192.
[CrossRef]


[6] A. Purnachandra Rao, "RTOS based automatic scheduling for military application", Imperial Journal of Interdisciplinary Research (IJIR) Vol.2, Issue-2, 2016, ISSN: 2454-1362.

[7] T. N. Bao Anh, S. L. Tan, "Survey and performance evaluation of RTOS for small microcontrollers", Micro, IEEE Computer Society, ISSN: 0272-1732, 21 August 2009.

[8] N. C. Gaitan, V. G. Gaitan, E.E. (Ciobanu) Moisuc, "Improving interrupt handling in the nMPRA", 12th International Conference on Development and Application Systems, Suceava, Romania, May 15-17, 2014, ISBN: 978-1-4799-5094-2/14 IEEE, pp.: 11-15.
[CrossRef] [SCOPUS Times Cited 5]


[9] E. E. (Ciobanu) Moisuc, Al. B. Larionescu, V. G. Gaitan, "Hardware event treating in nMPRA", 12th International Conference on Development and Application Systems, Suceava, Romania, May 15-17, 2014, ISBN: 978-1-4799-5094-2/14 IEEE, pp.: 66-69.
[CrossRef] [SCOPUS Times Cited 5]


[10] E. E. (Ciobanu) Moisuc, Al. B. Larionescu, I. Ungurean, "Hardware event handling in the hardware real-time", 18th International Conference on System Theory, Control and Computing to be held in Sinaia, Romania, October 17-19, 2014, ISBN: 978-1-4799-4600-6 ©2014 IEEE, pp.: 54-58.
[CrossRef] [SCOPUS Times Cited 3]


[11] L. Andries, V. G. Gaitan, "Dual priority scheduling algorithm used in the nMPRA microcontrollers", 18th International Conference on System Theory, Control and Computing to be held in Sinaia, Romania, October 17-19, 2014, ISBN: 978-1-4799-4600-6 IEEE.
[CrossRef] [SCOPUS Times Cited 3]


[12] K. M. Mallachiev, N. V. Pakulin, A.V. Khoroshilov, "Design and architecture of real-time operating system", Trudy ISP RAN /Proc. ISP RAS, 2016, vol. 28, no 2, pp. 181-192.
[CrossRef]


[13] Shweta Ohri, "Hardware architecture of a RTOS", International Journal of Engineering Research and General Science Volume 4, Issue 2, March-April, 2016, ISSN 2091-2730.

[14] M. Ramesha, "Design and Implementation of fully pipelined 64-point FFT Processor in a FPGA", International Journal of Applied Engineering Research, ISSN: 0973-4562 Volume 11, Number 6, 2016, pp.: 3940-3943 © Research India Publications.

[15] Kirat Pal Singh , Shiwani Dod, "Performance improvement in MIPS pipeline processor based on FPGA", International Journal of Engineering Technology, Management and Applied Sciences, January 2016, Volume 4, Issue 1, ISSN: 2349-4476.

[16] E. Dodiu, V. G. Gaitan, A. Graur, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – architecture description", IEEE 35’th Jubilee International Convention on Information and Communication Technology, Electronics and Microelectronics, Croatia, May 2012, ISBN: 978-1-4673-2577-6.

[17] E. Dodiu and V. G. Gaitan, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – concept and theory of operation", 2012 IEEE EIT International Conference on Electro-Information Technology, Indianapolis, USA, 6-8 May 2012, ISBN: 978-1-4673-0818-2, ISSN: 2154-0373.
[CrossRef] [SCOPUS Times Cited 13]


[18] B. C. Alecsa, "FPGA implementation of a matrix structure for integer division", Proceedings of the 3rd International Symposium on Electrical and Electronics Engineering, Galati, Romania, 2010, ISBN: 978-1-4244-8406-5 IEEE.
[CrossRef] [SCOPUS Times Cited 3]


[19] K. Singh, S. Parmar, "Design of high performance MIPS cryptography processor based on T-DES algorithm", International Journal of Engineering Research & Technology (IJERT), Vol. 1 Issue 3, May - 2012 ISSN: 2278-0181, pp.: 778-793.

[20] C. A. Tanase, "An approach of MPRA technique over ARM cache architecture", 13th International Conference on Development and Application Systems (AECE), Suceava, Romania, 2016, ISBN: 978-1-5090-1993-9/16 IEEE, pp. 86-90.
[CrossRef] [SCOPUS Times Cited 2]


[21] L. Li, G. Zhou, B. Fiethe, H. Michalik, B. Osterloh, "Efficient implementation of the CCSDS 122.0-B-1 compression standard on a spacequalified Field Programmable Gate Array", Journal of Applied Remote Sensing, vol. 7, no. 1, 7(1) 074595, 2013,
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 6]


[22] D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sarture, D. Dolman, "Airborne demonstration of FPGA implementation of fast lossless hyperspectral data compression system" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), July 2014, ISSN: 978-1-4799-5357-8
[CrossRef] [SCOPUS Times Cited 9]




References Weight

Web of Science® Citations for all references: 20 TCR
SCOPUS® Citations for all references: 62 TCR

Web of Science® Average Citations per reference: 1 ACR
SCOPUS® Average Citations per reference: 3 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-06-18 22:19 in 104 seconds.




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Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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