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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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ABC Algorithm based Fuzzy Modeling of Optical Glucose Detection, SARACOGLU, O. G., BAGIS, A., KONAR, M., TABARU, T. E.
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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

2017-Jan-30
We have the confirmation Advances in Electrical and Computer Engineering will be included in the Gale database.

2016-Dec-17
IoT is a new emerging technology domain which will be used to connect all objects through the Internet for remote sensing and control. IoT uses a combination of WSN (Wireless Sensor Network), M2M (Machine to Machine), robotics, wireless networking, Internet technologies, and Smart Devices. We dedicate a special section of Issue 2/2017 to IoT. Prospective authors are asked to make the submissions for this section no later than the 31st of March 2017, placing "IoT - " before the paper title in OpenConf.

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  3/2017 - 10

Enhanced Interrupt Response Time in the nMPRA based on Embedded Real Time Microcontrollers

GAITAN, N. C.
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,677 KB) | Citation | Downloads: 43 | Views: 62

Author keywords
architecture, operating systems, registers, scheduling, software

References keywords
gaitan(14), hardware(12), systems(8), time(7), architecture(7), real(6), nmpra(6), icstcc(6), control(6), theory(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-08-31
Volume 17, Issue 3, Year 2017, On page(s): 77 - 84
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.03010
SCOPUS ID: 85028523573

Abstract
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In any real-time operating system, task switching and scheduling, interrupts, synchronization and communication between processes, represent major problems. The implementation of these mechanisms through software generates significant delays for many applications. The nMPRA (Multi Pipeline Register Architecture) architecture is designed for the implementation of real-time embedded microcontrollers. It supports the competitive execution of n tasks, enabling very fast switching between them, with a usual delay of one machine cycle and a maximum of 3 machine cycles, for the memory-related work instructions. This is because each task has its own PC (Program Counter), set of pipeline registers and a general registers file. The nMPRA is provided with an advanced distributed interrupt controller that implements the concept of interrupts as threads. This allows the attachment of one or more interrupts to the same task. In this context, the original contribution of this article is to presents the solutions for improving the response time to interrupts when a task has attached a large number of interrupts. The proposed solutions enhance the original architecture for interrupts logic in order to transfer control, to the interrupt handler as soon as possible, and to create an interrupt prioritization at task level.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [Web of Science Times Cited 27] [SCOPUS Times Cited 32]


[2] M. Shahbazi, P. Poure, S. Saadate, M. R. Zolghadri, "FPGA-Based Reconfigurable Control for Fault-Tolerant Back-to-Back Converter Without Redundancy," IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3360–3371, Aug. 2013.
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[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 25]


[5] V. G. Gaitan, N. C. Gaitan, I. Ungurean, "CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661–1674, Sept. 2015.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 6]


[6] M. Zimmer, D. Broman, C. Shaver, E. A. Lee, "FlexPRET: A processor platform for mixed-criticality systems," in 20th IEEE Real-Time and Embedded Technology and Applications Symposium - RTAS, pp. 101–110, Apr. 2014.
[CrossRef] [SCOPUS Times Cited 21]


[7] E. Dodiu, V. G. Gaitan, A. Graur, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – architecture description", in IEEE 35’th Jubilee International Convention on Information and Communication Technology, Electronics and Microelectronics, Croatia, pp. 859-864, 24 May 2012.

[8] E. Dodiu, V. G. Gaitan, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers – concept and theory of operation," in IEEE EIT International Conference on Electro-Information Technology, Indianapolis, USA, pp. 1–5, May 2012.
[CrossRef] [SCOPUS Times Cited 11]


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[CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 17]


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[CrossRef]


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[13] D. Andrews, W. Peck, J. Agron, K. Preston, E. Komp, M. Finley, R. Sass, "hthreads: a hardware/software co-designed multithreaded RTOS kernel", Emerging Technologies and Factory Automation, 2005. ETFA 2005. 10th IEEE Conference on, vol.2, pp.338, 19-22 Sept. 2005.
[CrossRef]


[14] N. C. Gaitan, V. G. Gaitan, E.-E. (Ciobanu) Moisiuc: "Improving Interrupt Handling in the nMPRA", In Development and Application Systems (DAS), 2014 International Conference on. IEEE, pp. 11-15, 15–17 May, 2014.
[CrossRef] [SCOPUS Times Cited 4]


[15] C. Kyrkou, T. Theocharides, "A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines," in IEEE Transactions on Computers, vol. 61, no. 6, pp. 831-842, June 2012.
[CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 30]


[16] N. C. Gaitan, I. Zagan, V. G. Gaitan, "Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation," International Journal of Advanced Computer Science and Applications – IJACSA, vol. 6, no. 4, 2015.
[CrossRef]


[17] L. Andries, G. Gaitan, "Dual priority scheduling algorithm used in the nMPRA microcontrollers: Subtitle as needed (paper subtitle)," 2014 18th International Conference on System Theory, Control and Computing (ICSTCC), Sinaia, 2014, pp. 43-47.
[CrossRef] [SCOPUS Times Cited 2]


[18] E. E. C. Moisuc, A. B. Larionescu, I. Ungurean, "Hardware event handling in the hardware real-time operating systems," 2014 18th International Conference on System Theory, Control and Computing (ICSTCC), Sinaia, 2014, pp. 54-58.
[CrossRef] [SCOPUS Times Cited 2]


[19] I. Zagan, V. G. Gaitan, "Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy," Advances in Electrical and Computer Engineering, vol.16, no.4, pp.45-50, 2016,
[CrossRef] [Full Text] [Web of Science Times Cited 2] [SCOPUS Times Cited 2]


[20] E. E. Moisuc, A. B. Larionescu, V. G. Gaitan, "Hardware Event Treating in nMPRA," in 12rt International Conference on Development and Application Systems – DAS, Suceava, Romania, pp. 66-69, 15–17 May, 2014.
[CrossRef] [SCOPUS Times Cited 4]


[21] A. Kalyansundar, R. Chattopadhyay, "A Novel Approach to Hardware Architecture Design and Advanced Optimization Techniques for Time Critical Applications," 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, 2008, pp. 9-15.
[CrossRef] [Web of Science Record] [SCOPUS Times Cited 1]


[22] I. Zagan, V. G. Gaitan, "Schedulability analysis of nMPRA processor based on multithreaded execution," 2016 International Conference on Development and Application Systems (DAS), Suceava, 2016, pp. 130-134.
[CrossRef]


[23] L. Andries, V. G. Gaitan, E. E. Moisuc, "Programming paradigm of a microcontroller with hardware scheduler engine and independent pipeline registers - a software approach," 2015 19th International Conference on System Theory, Control and Computing (ICSTCC), Cheile Gradistei, 2015, pp. 705-710.
[CrossRef]


[24] I. Zagan, V. G. Gaitan, "Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy," Advances in Electrical and Computer Engineering, vol.16, no.4, pp.45-50, 2016,
[CrossRef] [Full Text] [Web of Science Times Cited 2] [SCOPUS Times Cited 2]




References Weight

Web of Science® Citations for all references: 158 TCR
SCOPUS® Citations for all references: 249 TCR

Web of Science® Average Citations per reference: 6 ACR
SCOPUS® Average Citations per reference: 10 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-09-25 10:47 in 401 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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