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JCR Impact Factor: 0.699
JCR 5-Year IF: 0.674
Issues per year: 4
Current issue: May 2018
Next issue: Aug 2018
Avg review time: 108 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2018-Jun-27
Clarivate Analytics published the InCites Journal Citations Report for 2017. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.699, and the JCR 5-Year Impact Factor is 0.674.

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

Read More »


    
 

  4/2015 - 2

Hardware Accelerators for Data Sort in All Programmable Systems-on-Chip

SKLYAROV, V. See more information about SKLYAROV, V. on SCOPUS See more information about SKLYAROV, V. on IEEExplore See more information about SKLYAROV, V. on Web of Science, SKLIAROVA, I. See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,276 KB) | Citation | Downloads: 434 | Views: 1,225

Author keywords
FPGA, system-on-chip, sorting, parallel processing, performance and resources evaluation

References keywords
sorting(13), link(9), systems(8), programmable(7), zynq(6), networks(6), xilinx(5), sklyarov(5), skliarova(5), high(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-11-30
Volume 15, Issue 4, Year 2015, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.04002
Web of Science Accession Number: 000368499800002
SCOPUS ID: 84949995957

Abstract
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Full text preview
The paper analyzes and evaluates architectures of the most efficient hardware accelerators for data sort in FPGA and all programmable systems-on-chip (such as devices from the Xilinx Zynq-7000 family). The following novel methods are proposed and discussed: 1) data sorting in hardware that is executed concurrently with getting inputs through single or multiple ports; 2) a technique allowing rational compromise between the cost and the latency of the circuit to be achieved. Both methods are targeted to hardware/software co-design and permit the best solution to be found for different requirements within pre-defined constraints. The results of experiments, implementations, and rigorous comparisons demonstrate high efficiency and broad applicability of the proposed methods for wide range of practical applications.


References | Cited By  «-- Click to see who has cited this paper

[1] Xilinx, Inc., Zynq-7000 All Programmable SoC Technical Reference Manual, 2014. [Online] Available: Temporary on-line reference link removed - see the PDF document

[2] L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book, University of Strathclyde, 2014.

[3] L. Hao and G. Stitt, "Bandwidth-Sensitivity-Aware Arbitration for FPGAs," IEEE Embedded Systems Letters, vol. 4, no. 3, 2012, pp. 73-76.
[CrossRef] [SCOPUS Times Cited 5]


[4] D.G. Bailey, Design for Embedded Image Processing on FPGAs, John Wiley and Sons, 2011.
[CrossRef] [SCOPUS Times Cited 163]


[5] V. Sklyarov, I. Skliarova, A. Barkalov, and L. Titarenko, Synthesis and Optimization of FPGA-based Systems, Springer, 2014.
[CrossRef] [SCOPUS Record]


[6] A. Cristo, K. Fisher, A.J. Gualtieri, R.M. Pérez, and P. Martínez, "Optimization of Processor-to-Hardware Module Communications on Spaceborne Hybrid FPGA-based Architectures," IEEE Embedded Systems Letters, vol. 5, no. 4, 2013, pp. 77-80.
[CrossRef] [SCOPUS Times Cited 5]


[7] A. Canedo, H. Ludwig, and M.A. Al Faruque, "High Communication Throughput and Low Scan Cycle Time with Multi/Many-Core Programmable Logic Controllers," IEEE Embedded Systems Letters, vol. 6, no. 2, 2014, pp. 21-24.
[CrossRef] [SCOPUS Times Cited 12]


[8] M. Santarini, "All Eyes on Zynq SoC for Smart Vision," XCell Journal, issue 83, 2013, pp. 8-15. [Online] Available: Temporary on-line reference link removed - see the PDF document

[9] C. Dick, "Xilinx All Programmable Devices Enable Smarter Wireless Networks," XCell Journal, issue 83, 2013, pp. 16-23. [Online] Available: Temporary on-line reference link removed - see the PDF document

[10] J. Silva, V. Sklyarov, and I. Skliarova, "Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip," IEEE Embedded Systems Letters, vol. 7, no. 1, 2015, pp. 31-34.
[CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 21]


[11] Xilinx, Inc., Vivado Design Suite Guides, 2015. [Online] Available: Temporary on-line reference link removed - see the PDF document

[12] Xilinx, Inc., Zynq-7000 All Programmable SoC Software Developers Guide, 2015. [Online] Available: Temporary on-line reference link removed - see the PDF document

[13] V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson, and C. Cardoso, Hardware/Software Co-design for Programmable Systems-on-Chip, TUT Press, 2014.

[14] Xilinx, Inc., Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[15] D.E. Knuth, The Art of Computer Programming. Sorting and Searching, vol. III, Addison-Wesley, New York 2011.

[16] R. Mueller, J. Teubner, and G. Alonso, "Sorting Networks on FPGAs," The International Journal on Very Large Data Bases, vol. 21, no. 1, 2012, pp. 1-23.
[CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 74]


[17] M. Zuluada, P. Milder, and M. Puschel, "Computer Generation of Streaming Sorting Networks," in Proc. 49th Design Automation Conference, San Francisco, USA, 2012, pp. 1245-1253.
[CrossRef] [SCOPUS Times Cited 27]


[18] R.D. Chamberlain and N. Ganesan, "Sorting on Architecturally Diverse Computer Systems," in Proc. 3rd Int. Workshop on High-Performance Reconfigurable Computing Technology and Applications, USA, 2009, pp. 39-46.
[CrossRef] [SCOPUS Times Cited 23]


[19] D. Koch and J. Torresen, "FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting", in Proc. 19th ACM/SIGDA Int. Symposium on Field Programmable Gate Arrays, USA, 2011, pp. 45-54.
[CrossRef] [SCOPUS Times Cited 80]


[20] P. Kipfer, and R. Westermann, "Improved GPU Sorting," in GPU Gems 2: programming techniques for high-performance graphics and general-purpose computation, M. Pharr (ed.), 2005. [Online] Available: Temporary on-line reference link removed - see the PDF document

[21] G. Gapannini, F. Silvestri, and R. Baraglia, "Sorting on GPU for large scale datasets: A thorough comparison," Information Processing and Management, vol. 48, no. 5, 2012, pp. 903-917.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 16]


[22] C. Grozea, Z. Bankovic, and P. Laskov, "FPGA vs. Multi-Core CPUs vs. GPUs: Hands-On Experience with a Sorting Application," in Facing the Multicore-Challenge, R. Keller, D. Kramer, and J.P. Weiss (eds.), Springer-Verlag, 2010, pp. 105-117.
[CrossRef] [SCOPUS Record]


[23] M. Edahiro, "Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration," in Proc. 18th Asia and South Pacific Design Automation Conf., Japan, 2009, pp. 230-233.
[CrossRef] [SCOPUS Times Cited 14]


[24] K.E. Batcher, "Sorting networks and their applications," in Proc. American Federation of Information Processing Societies (AFIPS) Spring Joint Computer Conf., USA, 1968, pp. 307-314.
[CrossRef]


[25] S.W. Al-Haj Baddar and K.E. Batcher, Designing Sorting Networks. A New Paradigm, Springer, 2011.
[CrossRef] [Web of Science Times Cited 16]


[26] V. Sklyarov and I. Skliarova, "High-performance implementation of regular and easily scalable sorting networks on an FPGA," Microprocessors and Microsystems, vol. 38, no. 5, 2014, pp. 470-484.
[CrossRef] [Web of Science Times Cited 23] [SCOPUS Times Cited 29]


[27] V. Sklyarov and I. Skliarova, "Fast regular circuits for network-based parallel data processing," Advances in Electrical and Computer Engineering, vol. 13, no. 4, 2013, pp. 47-50.
[CrossRef] [Full Text] [Web of Science Times Cited 10] [SCOPUS Times Cited 10]


[28] Digilent Inc., Nexys4™ FPGA board reference manual, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[29] Avnet, Inc., ZedBoard Hardware User’s Guide, 2014. [Online] Available: Temporary on-line reference link removed - see the PDF document



References Weight

Web of Science® Citations for all references: 120 TCR
SCOPUS® Citations for all references: 479 TCR

Web of Science® Average Citations per reference: 4 ACR
SCOPUS® Average Citations per reference: 16 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-07-21 13:53 in 122 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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