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JCR Impact Factor: 0.595
JCR 5-Year IF: 0.661
Issues per year: 4
Current issue: Aug 2017
Next issue: Nov 2017
Avg review time: 76 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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Wind Speed Prediction with Wavelet Time Series Based on Lorenz Disturbance, ZHANG, Y., WANG, P., CHENG, P., LEI, S.
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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

2017-Jan-30
We have the confirmation Advances in Electrical and Computer Engineering will be included in the Gale database.

2016-Dec-17
IoT is a new emerging technology domain which will be used to connect all objects through the Internet for remote sensing and control. IoT uses a combination of WSN (Wireless Sensor Network), M2M (Machine to Machine), robotics, wireless networking, Internet technologies, and Smart Devices. We dedicate a special section of Issue 2/2017 to IoT. Prospective authors are asked to make the submissions for this section no later than the 31st of March 2017, placing "IoT - " before the paper title in OpenConf.

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  1/2015 - 5

An Evolutionary Approach to the Soft Error Mitigation Technique for Cell-Based Design

PARK, J. K. See more information about PARK, J. K. on SCOPUS See more information about PARK, J. K. on IEEExplore See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (789 KB) | Citation | Downloads: 277 | Views: 1,263

Author keywords
soft error mitigation, single event transient, cell-based design, cell sizing, hybrid genetic algorithm

References keywords
soft(16), error(13), systems(8), design(8), analysis(8), rate(7), designs(7), circuits(6), logic(5), level(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 33 - 40
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01005
Web of Science Accession Number: 000352158600005
SCOPUS ID: 84924812869

Abstract
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In this paper, we present a soft error mitigation algorithm that searches for the proper gate sizes within constrained gate-level designs. The individual gate sizing has an impact on the former optimization results and degrades the quality of the solution. In order to address this inefficiency, we utilize a modified topological sort that preserves the preceding local optima. Using a new local searcher, a hybrid genetic optimization technique for soft error mitigation is proposed. This evolutionary search algorithm has general genetic operators: the initialization of the population, crossover, mutation and selection operators. The local searcher consists of two subsequent heuristics. These search algorithms make the individual chromosome move to better search regions in a short time and then, the population acquires various candidates for the global optimum with the help of other genetic operators. The experiments show that the proposed genetic algorithm achieves an approximately 90% reduction in the number of soft errors when compared to the conventional greedy approach with at most 30% overhead for the area and critical path delay.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 27]


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[CrossRef] [SCOPUS Times Cited 6]


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[CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 83]


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[7] J. K. Park, H. S. Choi and J. T. Kim, "A Soft Error Analysis Tool for High-Speed Digital Designs," Proc. of 2nd Int. conf. on Ubiquitous Information Management and Communication, pp. 280-282, 2008.
[CrossRef] [SCOPUS Times Cited 4]


[8] S. Kwon, J. K. Park and J. T. Kim, "An approximated soft error analysis technique for gate-level designs," IEICE Electronics Express, vol. 11, no. 10, pp. 1-7, 2014.
[CrossRef] [Web of Science Record] [SCOPUS Times Cited 1]


[9] H-K. Peng, C. H-P. Wen and B. Jayanta, "On soft error rate analysis of scaled CMOS designs: a statistical perspective," Proc. of IEEE/ACM Int’l Conf. on Computer-Aided Design, pp. 157-163, 2009.
[CrossRef]


[10] Y-H. Kuo, H-K. Peng and C. H-P. Wen, "Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models." Proc. of 11th Int’l symposium on Quality Electronic Design (ISQED), pp. 831-838, 2010.
[CrossRef] [SCOPUS Times Cited 19]


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[CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 16]


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[CrossRef] [Web of Science Times Cited 44]


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[14] H. Asadi and M. Tahoori, "Soft error hardening for logic-level designs," Proc. of IEEE Symp. on In Circuits and Systems, 2006.
[CrossRef]


[15] Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, "Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance," IEEE Trans. on Very Large Scale Integration Systems, vol. 14, no. 5, pp. 514-524, 2006.
[CrossRef] [Web of Science Times Cited 46] [SCOPUS Times Cited 62]


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[CrossRef]


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[CrossRef] [SCOPUS Times Cited 123]




References Weight

Web of Science® Citations for all references: 1,150 TCR
SCOPUS® Citations for all references: 1,784 TCR

Web of Science® Average Citations per reference: 50 ACR
SCOPUS® Average Citations per reference: 78 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-09-15 22:18 in 141 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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