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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 644266260
doi: 10.4316/AECE


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2016-Jun-14
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  2/2014 - 11

Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

SKLYAROV, V. See more information about SKLYAROV, V. on SCOPUS See more information about SKLYAROV, V. on IEEExplore See more information about SKLYAROV, V. on Web of Science, SKLIAROVA, I. See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,071 KB) | Citation | Downloads: 572 | Views: 1,813

Author keywords
hamming weight counter, hamming weight comparator, field-programmable gate array, digital signal processing slice, hardware accelerator, on-chip architecture

References keywords
link(10), hamming(6), circuits(6), systems(5), skliarova(5), sklyarov(4), parallel(4), fpga(4), digital(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 63 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02011
Web of Science Accession Number: 000340868100011
SCOPUS ID: 84901843912

Abstract
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Full text preview
This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP) slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL) specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations). Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.


References | Cited By  «-- Click to see who has cited this paper

[1] B. Parhami, "Efficient Hamming weight comparators for binary vectors based on accumulative and up/down parallel counters," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, 2009, pp. 167-171.
[CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 17]


[2] V. Pedroni, "Compact Hamming-comparator-based rank order filter for digital VLSI and FPGA implementations," in Proc. IEEE Int. Symp. on Circuits and Systems, vol. 2, Canada, 2004, pp. 585-588.
[CrossRef]


[3] K. Chen, "Bit-serial realizations of a class of nonlinear filters based on positive Boolean functions," IEEE Transactions on Circuits and Systems, vol. 36, no. 6, 1989, pp. 785-794.
[CrossRef] [SCOPUS Times Cited 65]


[4] P. D. Wendt, E. J. Coyle, and N.C. Gallagher, "Stack filters," IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 34, no. 4, 1986, pp. 898-908.
[CrossRef] [SCOPUS Times Cited 366]


[5] M. Storace and T. Poggi, "Digital architectures realizing piecewise-linear multivariate functions: two FPGA implementations," Int. Journal of Circuit Theory and Applications, vol. 39, no. 1, 2011, pp. 1-15.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 31]


[6] K. Asada, S. Kumatsu, and M. Ikeda, "Associative memory with minimum Hamming distance detector and its application to bus data encoding," in Proc. IEEE Asia-Pacific Application-Specific Integrated Circuits Conf., Korea, 1999, pp. 16-18.

[7] C. Barral, J. S. Coron, and D. Naccache, "Externalized fingerprint matching," in Proc. Int. Conf. on Biometric Authentication, Hong Kong, 2004, pp. 309-315.
[CrossRef]


[8] A. Zakrevskij, Y. Pottosin, and L. Cheremisiniva, Combinatorial Algorithms of Discrete Mathematics, TUT Press, 2008.

[9] I. Skliarova and A. B. Ferrari, "A Software/reconfigurable hardware SAT solver," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4, 2004, pp. 408-419.
[CrossRef] [Web of Science Times Cited 27] [SCOPUS Times Cited 36]


[10] D. E. Knuth, The Art of Computer Programming, vol. 3: Sorting and Searching, Addison-Wesley, 2011.

[11] V. Sklyarov and I. Skliarova, "Digital Hamming weight and distance analyzers for binary vectors and matrices," Int. Journal of Innovative Computing, Information and Control, vol. 9, no. 12, 2013, pp. 4825-4849.

[12] J. D. Davis, Z. Tan, F. Yu, and L. Zhang, "A practical reconfigurable hardware accelerator for Boolean satisfiability solvers," in Proc. 45th ACM/IEEE Design Automation Conf., USA, 2008, pp. 780-785.
[CrossRef]


[13] D. Cullina, A.A. Kulkarni, and N. Kiyavash, "A coloring approach to constructing deletion correcting codes from constant weight subgraphs," in Proc. of IEEE Int. Symp. on Information Theory, UK, 2012.
[CrossRef] [SCOPUS Times Cited 7]


[14] Intel, Corp., Intel® SSE4 Programming Reference, 2007. [Online] Available: Temporary on-line reference link removed - see the PDF document

[15] ARM, Ltd., NEON™ Version: 1.0 Programmer’s Guide, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[16] Dalke Scientific Software, LLC, Faster population counts, 2011. [Online] Available: Temporary on-line reference link removed - see the PDF document

[17] R. Ramanarayanan, S. Mathew, V. Erraguntla, R. Krishnamurthy, and S. Gueron, "A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm," in Proc. 21st Int. Conf. on VLSI Design, India, 2008.

[18] L. Field, T. Barnie, J. Blundy, R.A. Brooker, D. Keir, E. Lewi, and K. Saunders, "Integrated field, satellite and petrological observations of the November 2010 eruption of Erta Ale," Bulletin of Volcanology, vol. 74, no. 10, 2012, pp. 2251-2271.

[19] V. Sklyarov and I. Skliarova, "Fast Regular Circuits for Network-based Parallel Data Processing," Advances in Electrical and Computer Engineering, vol. 13, no. 4, 2013, pp. 47-50.
[CrossRef] [Full Text] [Web of Science Times Cited 7] [SCOPUS Times Cited 7]


[20] Digilent, Inc., Nexys4™ FPGA board reference manual, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[21] Xilinx, Inc., 7 Series DSP48E1 Slice User Guide, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[22] V. Sklyarov and I. Skliarova, "Design and implementation of counting networks," Computing, 2013.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 3]


[23] V. Sklyarov and I. Skliarova, Parallel Processing in FPGA-based Digital Circuits and Systems, TUT Press, 2013.

[24] S. J. Piestrak, "Efficient Hamming weight comparators of binary vectors," Electronic Letters, vol. 43, no. 11, 2007, pp. 611-612.

[25] V. A. Pedroni, "Compact fixed-threshold and two-vector Hamming comparators," Electronic Letters, vol. 39, no. 24, 2003, pp. 1705-1706.

[26] R. Mueller, J. Teubner, and G. Alonso, "Sorting Networks on FPGAs," The Int. Journal on Very Large Data Bases, vol. 21, no. 1, 2012, pp. 1-23.

[27] Avnet, Inc., ZedBoard (Zynq™ Evaluation and Development) Hardware User’s Guide, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[28] Digilent, Inc., ZyBo Reference Manual, 2014. [Online] Available: Temporary on-line reference link removed - see the PDF document

[29] M. Sadri, C. Weis, N. Wehn, and L. Benini, "Energy and Performance Exploration of Accelerator Coherency Port Using Xilinx ZYNQ," in Proc. 10th FPGAworld Conf., Copenhagen and Stockholm, 2013.

[30] Digilent, Inc., PmodKYPD Reference Manual, 2011. [Online] Available: Temporary on-line reference link removed - see the PDF document

[31] S. E. Anderson, Counting bits set, in parallel. [Online] Available: Temporary on-line reference link removed - see the PDF document

[32] Xilinx, Inc., OS and Libraries Document Collection, 2010. [Online] Available: Temporary on-line reference link removed - see the PDF document



References Weight

Web of Science® Citations for all references: 76 TCR
SCOPUS® Citations for all references: 532 TCR

Web of Science® Average Citations per reference: 2 ACR
SCOPUS® Average Citations per reference: 16 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2016-12-07 17:18 in 61 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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