|1/2014 - 3|
Adaptive Neuro-fuzzy Inference System as Cache Memory Replacement PolicyCHUNG, Y. M. , HALIM, Z. A.
|Click to see author's profile on SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (723 KB) | Citation | Downloads: 406 | Views: 1,850|
cache memory, fuzzy neural networks, Takagi-Sugeno model, replacement policy, supervised learning
cache(12), fuzzy(10), systems(8), replacement(7), system(6), policies(5), performance(5), adaptive(5), neuro(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 15 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01003
Web of Science Accession Number: 000332062300003
SCOPUS ID: 84894609777
To date, no cache memory replacement policy that can perform efficiently for all types of workloads is yet available. Replacement policies used in level 1 cache memory may not be suitable in level 2. In this study, we focused on developing an adaptive neuro-fuzzy inference system (ANFIS) as a replacement policy for improving level 2 cache performance in terms of miss ratio. The recency and frequency of referenced blocks were used as input data for ANFIS to make decisions on replacement. MATLAB was employed as a training tool to obtain the trained ANFIS model. The trained ANFIS model was implemented on SimpleScalar. Simulations on SimpleScalar showed that the miss ratio improved by as high as 99.95419% and 99.95419% for instruction level 2 cache, and up to 98.04699% and 98.03467% for data level 2 cache compared with least recently used and least frequently used, respectively.
|References|||||Cited By «-- Click to see who has cited this paper|
| H. Ghasemzadeh, et al., "Modified pseudo LRU replacement algorithm," in Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems, pp. 370-376, 2006. |
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]
 W. A. Wong and J. L. Baer, "Modified LRU policies for improving second-level cache behavior," in Sixth International Symposium on High-Performance Computer Architecture, pp. 49-60, 2000.
 S. Gupta, et al., "Locality Principle Revisited: A Probability-Based Quantitative Approach," in IEEE 26th International Parallel & Distributed Processing Symposium (IPDPS), pp. 995-1009, 2012.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 4]
 L. Donghee, et al., "LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies," IEEE Transactions on Computers, vol. 50, pp. 1352-1361, 2001.
[CrossRef] [SCOPUS Times Cited 205]
 M. K. Qureshi, et al., "Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching," IEEE Micro, vol. 28, pp. 91-98, 2008.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 5]
 S. Kaxiras, et al., "Cache decay: exploiting generational behavior to reduce cache leakage power," in 28th Annual International Symposium on Computer Architecture, pp. 240-251, 2001.
[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 27]
 L. An-Chow, et al., "Dead-block prediction & dead-block correlating prefetchers," in 28th Annual International Symposium on Computer Architecture, pp. 144-154, 2001.
[CrossRef] [Web of Science Times Cited 39]
 M. Atique and M. S. Ali, "An Adaptive Neuro Fuzzy Inference System for Cache Replacement in Multimedia Operating System," in International Conference on Electrical and Computer Engineering, 2006 (ICECE '06). pp. 286-290, 2006.
[CrossRef] [SCOPUS Times Cited 2]
 O. Hammami, "Pipeline integration of neuro and fuzzy cache management techniques," in Proceedings of the Sixth IEEE International Conference on Fuzzy Systems, vol.2, pp. 653-658, 1997.
 W. Ali and S. M. Shamsuddin, "Neuro-fuzzy system in web client-side caching," in Expert Systems with Applications, vol. 38, no. 12, pp. 14715-14725, 2011.
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 12]
 M. S. Obaidat and H. Khalid, "Estimating neural networks-based algorithm for adaptive cache replacement," IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, vol. 28, pp. 602-611, 1998.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 10]
 K. Sedigheh, et al., "A Fuzzy Cache Replacement Policy and Its Experimental Performance Assessment," in Innovations in Information Technology, pp. 1-5, 2006.
[CrossRef] [SCOPUS Times Cited 1]
 J. S. R. Jang, "ANFIS: adaptive-network-based fuzzy inference system," IEEE Transactions on Systems, Man and Cybernetics, vol. 23, pp. 665-685, 1993.
[CrossRef] [Web of Science Times Cited 5094] [SCOPUS Times Cited 7568]
 JANG, J. S. R. & SUN, C. T. "Neuro-fuzzy modeling and control," Proceedings of the IEEE, vol. 83, no. 3, pp. 378-406, 1995.
[CrossRef] [Web of Science Times Cited 914] [SCOPUS Times Cited 1296]
 J. S. R. Jang, "Input selection for ANFIS learning," in Proceedings of the Fifth IEEE International Conference on Fuzzy Systems, 1996, vol.2, pp. 1493-1499
 T. Austin, et al., "SimpleScalar: An infrastructure for computer system modeling," Computer, vol. 35, pp. 59-67, 2002.
[CrossRef] [SCOPUS Times Cited 1049]
 K. Ganesan, et al., "Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics," Computer Performance Evaluation and Benchmarking, pp. 121-137, 2009.
[CrossRef] [SCOPUS Times Cited 3]
 A. A. Nair and L. K. John, "Simulation points for SPEC CPU 2006," in IEEE International Conference on Computer Design, pp. 397-403, 2008.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 7]
 R. Gupta and S. Tokekar, "Efficient Pair of Replacement Algorithms for L1 and L2 Cache for Matrix Multiplication," in IEEE International Advance Computing Conference, 2009. (IACC 2009), pp. 502-507, 2009.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]
 Z. Yuanyuan, et al., "Second-level buffer cache management," IEEE Transactions on Parallel and Distributed Systems, vol. 15, pp. 505-519, 2004.
[CrossRef] [Web of Science Times Cited 42] [SCOPUS Times Cited 77]
 M. Chaudhuri, "Pseudo-LIFO: The foundation of a new family of replacement policies for last-level caches," in 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 401-412, 2009.
[CrossRef] [SCOPUS Times Cited 22]
 L. Zhan-sheng, et al., "CRFP: A Novel Adaptive Replacement Policy Combined the LRU and LFU Policies," in IEEE 8th International Conference on Computer and Information Technology Workshops, pp. 72-79, 2008.
[CrossRef] [SCOPUS Times Cited 3]
 M. S. Haque, et al., "CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 126-133, 2011.
[CrossRef] [SCOPUS Times Cited 6]
 A. Milenkovic, et al., "A performance evaluation of memory hierarchy in embedded systems," in Proceedings of the 35th Southeastern Symposium on System Theory, pp. 427-431, 2003.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 4]
 Z. Qingbo and Z. Yuanyuan, "Power-aware storage cache management," IEEE Transactions on Computers, vol. 54, pp. 587-602, 2005.
[CrossRef] [SCOPUS Times Cited 87]
Web of Science® Citations for all references: 6,139 TCR
SCOPUS® Citations for all references: 10,392 TCR
Web of Science® Average Citations per reference: 236 ACR
SCOPUS® Average Citations per reference: 400 ACR
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references background updated on 2017-02-20 10:37 in 156 seconds.
Note1: Web of Science® is a registered trademark of Thomson Reuters.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.