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Adaptive Neuro-fuzzy Inference System as Cache Memory Replacement PolicyCHUNG, Y. M. , HALIM, Z. A.
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cache memory, fuzzy neural networks, Takagi-Sugeno model, replacement policy, supervised learning
cache(12), fuzzy(10), systems(8), replacement(7), system(6), policies(5), performance(5), adaptive(5), neuro(4)
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About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 15 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01003
Web of Science Accession Number: 000332062300003
SCOPUS ID: 84894609777
To date, no cache memory replacement policy that can perform efficiently for all types of workloads is yet available. Replacement policies used in level 1 cache memory may not be suitable in level 2. In this study, we focused on developing an adaptive neuro-fuzzy inference system (ANFIS) as a replacement policy for improving level 2 cache performance in terms of miss ratio. The recency and frequency of referenced blocks were used as input data for ANFIS to make decisions on replacement. MATLAB was employed as a training tool to obtain the trained ANFIS model. The trained ANFIS model was implemented on SimpleScalar. Simulations on SimpleScalar showed that the miss ratio improved by as high as 99.95419% and 99.95419% for instruction level 2 cache, and up to 98.04699% and 98.03467% for data level 2 cache compared with least recently used and least frequently used, respectively.
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| H. Ghasemzadeh, et al., "Modified pseudo LRU replacement algorithm," in Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems, pp. 370-376, 2006. |
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 13]
 W. A. Wong and J. L. Baer, "Modified LRU policies for improving second-level cache behavior," in Sixth International Symposium on High-Performance Computer Architecture, pp. 49-60, 2000.
 S. Gupta, et al., "Locality Principle Revisited: A Probability-Based Quantitative Approach," in IEEE 26th International Parallel & Distributed Processing Symposium (IPDPS), pp. 995-1009, 2012.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 9]
 L. Donghee, et al., "LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies," IEEE Transactions on Computers, vol. 50, pp. 1352-1361, 2001.
[CrossRef] [SCOPUS Times Cited 287]
 M. K. Qureshi, et al., "Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching," IEEE Micro, vol. 28, pp. 91-98, 2008.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 9]
 S. Kaxiras, et al., "Cache decay: exploiting generational behavior to reduce cache leakage power," in 28th Annual International Symposium on Computer Architecture, pp. 240-251, 2001.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 70]
 L. An-Chow, et al., "Dead-block prediction & dead-block correlating prefetchers," in 28th Annual International Symposium on Computer Architecture, pp. 144-154, 2001.
[CrossRef] [Web of Science Times Cited 63]
 M. Atique and M. S. Ali, "An Adaptive Neuro Fuzzy Inference System for Cache Replacement in Multimedia Operating System," in International Conference on Electrical and Computer Engineering, 2006 (ICECE '06). pp. 286-290, 2006.
[CrossRef] [SCOPUS Times Cited 2]
 O. Hammami, "Pipeline integration of neuro and fuzzy cache management techniques," in Proceedings of the Sixth IEEE International Conference on Fuzzy Systems, vol.2, pp. 653-658, 1997.
 W. Ali and S. M. Shamsuddin, "Neuro-fuzzy system in web client-side caching," in Expert Systems with Applications, vol. 38, no. 12, pp. 14715-14725, 2011.
[CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 19]
 M. S. Obaidat and H. Khalid, "Estimating neural networks-based algorithm for adaptive cache replacement," IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, vol. 28, pp. 602-611, 1998.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 10]
 K. Sedigheh, et al., "A Fuzzy Cache Replacement Policy and Its Experimental Performance Assessment," in Innovations in Information Technology, pp. 1-5, 2006.
[CrossRef] [SCOPUS Times Cited 1]
 J. S. R. Jang, "ANFIS: adaptive-network-based fuzzy inference system," IEEE Transactions on Systems, Man and Cybernetics, vol. 23, pp. 665-685, 1993.
[CrossRef] [Web of Science Times Cited 6733] [SCOPUS Times Cited 9308]
 JANG, J. S. R. & SUN, C. T. "Neuro-fuzzy modeling and control," Proceedings of the IEEE, vol. 83, no. 3, pp. 378-406, 1995.
[CrossRef] [Web of Science Times Cited 1134] [SCOPUS Times Cited 1568]
 J. S. R. Jang, "Input selection for ANFIS learning," in Proceedings of the Fifth IEEE International Conference on Fuzzy Systems, 1996, vol.2, pp. 1493-1499
 T. Austin, et al., "SimpleScalar: An infrastructure for computer system modeling," Computer, vol. 35, pp. 59-67, 2002.
 K. Ganesan, et al., "Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics," Computer Performance Evaluation and Benchmarking, pp. 121-137, 2009.
[CrossRef] [SCOPUS Times Cited 11]
 A. A. Nair and L. K. John, "Simulation points for SPEC CPU 2006," in IEEE International Conference on Computer Design, pp. 397-403, 2008.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 18]
 R. Gupta and S. Tokekar, "Efficient Pair of Replacement Algorithms for L1 and L2 Cache for Matrix Multiplication," in IEEE International Advance Computing Conference, 2009. (IACC 2009), pp. 502-507, 2009.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]
 Z. Yuanyuan, et al., "Second-level buffer cache management," IEEE Transactions on Parallel and Distributed Systems, vol. 15, pp. 505-519, 2004.
[CrossRef] [Web of Science Times Cited 56] [SCOPUS Times Cited 90]
 M. Chaudhuri, "Pseudo-LIFO: The foundation of a new family of replacement policies for last-level caches," in 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 401-412, 2009.
[CrossRef] [SCOPUS Times Cited 70]
 L. Zhan-sheng, et al., "CRFP: A Novel Adaptive Replacement Policy Combined the LRU and LFU Policies," in IEEE 8th International Conference on Computer and Information Technology Workshops, pp. 72-79, 2008.
[CrossRef] [SCOPUS Times Cited 10]
 M. S. Haque, et al., "CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 126-133, 2011.
[CrossRef] [SCOPUS Times Cited 8]
 A. Milenkovic, et al., "A performance evaluation of memory hierarchy in embedded systems," in Proceedings of the 35th Southeastern Symposium on System Theory, pp. 427-431, 2003.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 8]
 Z. Qingbo and Z. Yuanyuan, "Power-aware storage cache management," IEEE Transactions on Computers, vol. 54, pp. 587-602, 2005.
[CrossRef] [SCOPUS Times Cited 92]
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