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JCR Impact Factor: 0.595
JCR 5-Year IF: 0.661
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Next issue: Aug 2018
Avg review time: 105 days


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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
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2017-Jan-30
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  4/2013 - 8

Fast Regular Circuits for Network-based Parallel Data Processing

SKLYAROV, V. See more information about SKLYAROV, V. on SCOPUS See more information about SKLYAROV, V. on IEEExplore See more information about SKLYAROV, V. on Web of Science, SKLIAROVA, I. See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (714 KB) | Citation | Downloads: 324 | Views: 1,857

Author keywords
data processing, field-programmable gate arrays, parallel processing, reconfigurable architectures, sorting

References keywords
sorting(13), processing(6), parallel(5), programmable(4), ipdps(4), high(4), gpus(4), fpga(4), core(4), applications(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 47 - 50
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04008
Web of Science Accession Number: 000331461300008
SCOPUS ID: 84890199222

Abstract
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This paper is dedicated to the design, implementation, and evaluation of fast circuits executing operations that are frequently required in data processing which are: 1) discovering the maximum and minimum values in a given set of data; and 2) sorting data items. We found that minimizing the number of circuit components does not guarantee minimal hardware resources. This is because interconnections also influence the complexity significantly. Network-based circuits are often considered to be combinational. However, this does not mean that they are faster than sequential circuits solving the same problem because propagation delays can be considerable. We revised the existing network-based solutions and proposed regular circuits which provide a good compromise between hardware resources and performance.


References | Cited By  «-- Click to see who has cited this paper

[1] G. Gapannini, F. Silvestri, and R. Baraglia, "Sorting on GPU for large scale datasets: A through comparison," Information Processing and Management, 2012, vol. 48, no. 5, pp. 903-917.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 16]


[2] R. Mueller, J. Teubner, and G. Alonso, "Sorting Networks on FPGAs," The International Journal on Very Large Data Bases, vol. 21, no. 1, 2012, pp. 1-23.

[3] GPU Gems, Improved GPU Sorting. [Online] Available: Temporary on-line reference link removed - see the PDF document

[4] M. Zuluada, P. Milder, and M. Puschel, "Computer Generation of Streaming Sorting Networks," in Proc. 49th Design Automation Conf., San Francisco, June, 2012, pp. 1245-1253.
[CrossRef] [SCOPUS Times Cited 27]


[5] D. E. Knuth, The Art of Computer Programming. Sorting and Searching, vol. III. Addison-Wesley, 1973.

[6] K. E. Batcher, "Sorting networks and their applications," in Proc. AFIPS Spring Joint Computer Conf., USA, 1968, pp. 307-314.

[7] Xilinx Inc., Zynq-7000, All Programmable SoC, 2013. [Online] Available: Temporary on-line reference link removed - see the PDF document

[8] R. D. Chamberlain and N. Ganesan, "Sorting on Architecturally Diverse Computer Systems," in Proc. 3rd Int. Workshop on High-Performance Reconfigurable Computing Technology and Applications - HPRCTA'09, USA, 2009, pp. 39-46.
[CrossRef] [SCOPUS Times Cited 23]


[9] J. Ortiz and D. Andrews, "A Configurable High-Throughput Linear Sorter System," in Proc. of IEEE Int. Symp. on Parallel & Distributed Processing, April, 2010, pp. 1-8.
[CrossRef] [SCOPUS Times Cited 10]


[10] D.J. Greaves and S. Singh, "Kiwi: Synthesis of FPGA circuits from parallel programs," in Proc. 16th IEEE Int. Symp. on Field-Programmable Custom Computing Machines - FCCM'08, USA, 2008, pp. 3-12.
[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 53]


[11] S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach, "Accelerating Compute-Intensive Applications with GPUs and FPGAs," in Proc. Symp. on Application Specific Processors - SASP'08, USA, 2008, pp. 101-107.
[CrossRef] [Web of Science Times Cited 65] [SCOPUS Times Cited 148]


[12] R. Mueller, Data Stream Processing on Embedded Devices. Ph.D. thesis, ETH, Zurich, 2010.

[13] D. Koch and J. Torresen, "FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting," in Proc. 19th ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays - FPGA'11, USA, 2011, pp. 45-54.
[CrossRef] [Web of Science Times Cited 65] [SCOPUS Times Cited 148]


[14] V. Sklyarov, I. Skliarova, D. Mihhailov, and A. Sudnitson, "Implementation in FPGA of Address-based Data Sorting," in Proc. 21st Int. Conf. on Field-Programmable Logic and Applications - FPL'11, Greece, 2011, pp. 405-410.

[15] X. Ye, D. Fan, W. Lin, N. Yuan, and P. Ienne, "High Performance Comparison-Based Sorting Algorithm on Many-Core GPUs," in Proc. IEEE Int. Symp. on Parallel & Distributed Processing - IPDPS'10, USA, 2010, pp. 1-10.
[CrossRef] [SCOPUS Times Cited 32]


[16] N. Satish, M. Harris, and M. Garland, "Designing efficient sorting algorithms for manycore GPUs," in Proc. IEEE Int. Symp. on Parallel & Distributed Processing - IPDPS'09, Italy, 2009, pp. 1-10.
[CrossRef] [SCOPUS Times Cited 313]


[17] D. Cederman and P. Tsigas, "A practical quicksort algorithm for graphics processors," in Proc. 16th Annual European Symp. on Algorithms - ESA'08, Germany, 2008, pp. 246-258.

[18] C. Grozea, Z. Bankovic, and P. Laskov, "FPGA vs. Multi-Core CPUs vs. GPUs," in Facing the multicore-challenge, R. Keller, D. Kramer, and J.P. Weiss (Eds), Springer-Verlag Berlin, Heidelberg, 2010, pp. 105-117.
[CrossRef] [SCOPUS Times Cited 14]


[19] M. Edahiro, "Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration," in Proc. 18th Asia and South Pacific Design Automation Conf. - ASP-DAC'09, Japan, 2009, pp. 230-233.

[20] H. S. Stone, "Parallel Processing with the Perfect Shuffle," IEEE Transactions on Computers, vol. C-20, (2), 1971.
[CrossRef] [SCOPUS Times Cited 717]




References Weight

Web of Science® Citations for all references: 149 TCR
SCOPUS® Citations for all references: 1,501 TCR

Web of Science® Average Citations per reference: 7 ACR
SCOPUS® Average Citations per reference: 71 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-06-19 20:29 in 81 seconds.




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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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