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JCR Impact Factor: 0.459
JCR 5-Year IF: 0.442
Issues per year: 4
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Next issue: Feb 2017
Avg review time: 74 days


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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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FEATURED ARTICLE

Broken Bar Fault Detection in IM Operating Under No-Load Condition, RELJIC, D., JERKAN, D., MARCETIC, D., OROS, D.
Issue 4/2016

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  4/2013 - 3

A Cell Sizing Technique for Mitigating Logic Soft Errors in Gate-level Designs

PARK, J. K. See more information about PARK, J. K. on SCOPUS See more information about PARK, J. K. on IEEExplore See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (846 KB) | Citation | Downloads: 369 | Views: 2,063

Author keywords
single event transient, soft error, soft error mitigation, gate-level, gate sizing, cell sizing

References keywords
soft(16), error(15), design(9), circuits(6), combinational(5), analysis(5), systems(4), rate(4), logic(4), designs(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 13 - 18
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04003
Web of Science Accession Number: 000331461300003
SCOPUS ID: 84890160731

Abstract
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The effect of logic soft errors on the degradation of the reliability becomes more crucial in the case of nano-meter semiconductor designs. Several hardening techniques have been reported from the transistor- to system-level. In order to suppress the single event transients originating from logic gates, this paper presents an improved heuristic search utilizing the gate-sizing technique. The algorithm re-orders the gate-traversal to maintain the reduced soft error rates of the preceding logic gates. The preferential candidates for the two successive algorithms are the logic gates near the primary outputs and flip-flops, rather than those of the higher portions of block soft error rate. The proposed technique reduces the logic soft error rate by more than 60% compared to the existing method in 45nm CMOS cell designs.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [SCOPUS Times Cited 19]


[2] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo and T. Toba, "Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule," IEEE Trans. On Electron Devices, Vol.57, No.7, pp.1527-1537, 2010.
[CrossRef] [Web of Science Times Cited 116] [SCOPUS Times Cited 158]


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[CrossRef] [SCOPUS Times Cited 1]


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[CrossRef] [SCOPUS Times Cited 1]


[6] L. Xiao, W. Sheng and Z. Mao, "Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm," proc. of Design Automation Conference, pp.502-507, 2009.

[7] J. K. Park and J. T. Kim, "A soft error mitigation technique for constrained gate-level designs," IEICE Electronics Express, Vol.5, No.18, pp.698-704, 2008.

[8] N. M. Zivanov and D. Marculescu, "MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits," proc. of Design Automation Conference, pp.767-772, 2006.

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[10] H. Asadi and M. Tahoori, "Soft error hardening for logic-level designs," proc. of ISCAS, 2006.
[CrossRef]


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[CrossRef] [Web of Science Times Cited 44] [SCOPUS Times Cited 60]


[12] W. Kai-Chiang and D. Marculescu, "soft error rate reduction using redundancy addition and removal," proc. of ASPDAC, pp.559-564, 2008.
[CrossRef] [SCOPUS Times Cited 11]


[13] J. K. Park, H. S. Choi and J. T. Kim, "A Soft Error Analysis Tool for High-Speed Digital Designs," proc. of 2nd Int. conf. on Ubiquitous Information Management and Communication, pp.280-282, 2008.

[14] R. R. Rao, K. Chopra and D. T. Blaauw, "Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.26, No.3, 2007.
[CrossRef] [Web of Science Times Cited 44] [SCOPUS Times Cited 66]


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[CrossRef] [SCOPUS Times Cited 81]


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[CrossRef] [SCOPUS Times Cited 81]




References Weight

Web of Science® Citations for all references: 529 TCR
SCOPUS® Citations for all references: 891 TCR

Web of Science® Average Citations per reference: 25 ACR
SCOPUS® Average Citations per reference: 42 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references background updated on 2017-02-25 16:38 in 95 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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