|2/2013 - 5|
Self-Configurable FPGA-Based Computer SystemsMELNYK, A. , MELNYK, V.
|Click to see author's profile on SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (619 KB) | Citation | Downloads: 483 | Views: 2,637|
field programmable gate arrays, high performance computing, reconfigurable architectures, reconfigurable logic, self-configurable computer systems
link(12), reconfigurable(7), level(7), high(6), design(6), fpga(5), computing(5), system(4), melnyk(4), gupta(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-05-31
Volume 13, Issue 2, Year 2013, On page(s): 33 - 38
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.02005
Web of Science Accession Number: 000322179400005
SCOPUS ID: 84878904517
Method of information processing in reconfigurable computer systems is formulated and its improvements that allow an information processing efficiency to increase are proposed. New type of high-performance computer systems, which are named self-configurable FPGA-based computer systems and perform information processing according to this improved method, is proposed. The structure of self-configurable FPGA-based computer systems, rules of application of computer software and hardware means, which are necessary for these systems implementation, are described and their execution time characteristics are estimated. The directions for further works are discussed.
|References|||||Cited By «-- Click to see who has cited this paper|
| Scott Hauck, Andre DeHon. "Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation". Morgan Kaufmann, 2008. - 944 p.
 Melnyk A., Melnyk V. "Personal Supercomputers: Architecture, Design, Application". - Lviv National Polytechnic University Publishing, 2013. - 516 p.
 Christophe Bobda. "Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications". - Springer, 2010. - 362 p.
 T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk and P. Cheung. Reconfigurable Computing: Architectures, Design Methods, and Applications. IEE Proceedings on Computers and Digital Techniques 152 (2) pp.193-207 (2005).
[CrossRef] [Web of Science Times Cited 140]
 C-to-Verilog. Cirquit Design Automation. [Online] Available: Temporary on-line reference link removed - see the PDF document
 IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666-2011. 9 January 2012. - 638 p.
 Handel-C Synthesis Methodology - Mentor Graphics. [Online] Available: Temporary on-line reference link removed - see the PDF document
 Catapult LP for a Power Optimized ESL Hardware Realization Flow. [Online] Available: Temporary on-line reference link removed - see the PDF document
 DIMETalk. FPGA Development Tools. [Online] Available: Temporary on-line reference link removed - see the PDF document
 C-to-FPGA Tools form Impulse Accelerated Technologies. Impulse CoDeveloper C-to-FPGA Tools. [Online] Available: Temporary on-line reference link removed - see the PDF document
 ROCCC2.0. Jacquard Computing. [Online] Available: Temporary on-line reference link removed - see the PDF document
 A. Melnyk, A. Salo, V. Klymenko, L. Tsyhylyk. Chameleon - system for specialized processors high-level synthesis. Scientific-technical magazine of National Aerospace University "KhAI", Kharkiv, 2009. N5, pp. 189-195.
 Chameleon - the System-Level Design Solution. [Online] Available: Temporary on-line reference link removed - see the PDF document
 S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau. SPARK: a high-level synthesis framework for applying parallelizing compiler transformations. Proc. International Conference on VLSI Design, January 2003.
 Gupta, S., Gupta, R.K., Dutt, N.D., Nicolau, A.: SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Kluwer Academic, Dordrecht (2004).
 Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into an integrated processor with reconfigurable logic. Oct, 12 1999: US 5966534.
 Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic. Intel Mar, 16 2004: US 6708325.
 V. Melnyk, V. Stepanov, Z. Sarajrech. System of load balancing between host computer and reconfigurable accelerator. Proceedings "Computer systems and components" of Tchernivtsi National University. - Tchernivtsi. 2012. T. 3. Ed. 1. pp. 6-16.
 Ivor Horton. Beginning Visual C++ 2005. - John Wiley & Sons., 2005. - 1224 p.
 DRC Computer Corporation. RPU100-L60 DRC Reconfigurable Processor Unit. A breakthrough in coprocessor technology. [Online] Available: Temporary on-line reference link removed - see the PDF document
 H100 Series FPGA Application Accelerators. Version 1.9. September 2008. [Online] Available: Temporary on-line reference link removed - see the PDF document
 Celoxica Ltd. RCHTX-XV4 High Performance Computing (HPC) Application Acceleration Board Datasheet. Version 1.0. 2006. [Online] Available: Temporary on-line reference link removed - see the PDF document
 Relogix Assembler-to-C translator. [Online] Available: Temporary on-line reference link removed - see the PDF document
 Handel-C Language Reference Manual For DK Version 4. Celoxica Limited, 2005. - 348p.
 Agility Compiler for SystemC. Electronic System Level Behavioral Design & Synthesis Datasheet. 2005. [Online] Available: Temporary on-line reference link removed - see the PDF document
Web of Science® Citations for all references: 140 TCR
SCOPUS® Citations for all references: 0
Web of Science® Average Citations per reference: 5 ACR
SCOPUS® Average Citations per reference: 0
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references updated on 2018-03-20 02:38 in 11 seconds.
Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.