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JCR Impact Factor: 0.459
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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  2/2013 - 5

Self-Configurable FPGA-Based Computer Systems

MELNYK, A. See more information about MELNYK, A. on SCOPUS See more information about MELNYK, A. on IEEExplore See more information about MELNYK, A. on Web of Science, MELNYK, V. See more information about MELNYK, V. on SCOPUS See more information about MELNYK, V. on SCOPUS See more information about MELNYK, V. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (619 KB) | Citation | Downloads: 451 | Views: 2,225

Author keywords
field programmable gate arrays, high performance computing, reconfigurable architectures, reconfigurable logic, self-configurable computer systems

References keywords
link(12), reconfigurable(7), level(7), high(6), design(6), fpga(5), computing(5), system(4), melnyk(4), gupta(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-05-31
Volume 13, Issue 2, Year 2013, On page(s): 33 - 38
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.02005
Web of Science Accession Number: 000322179400005
SCOPUS ID: 84878904517

Abstract
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Full text preview
Method of information processing in reconfigurable computer systems is formulated and its improvements that allow an information processing efficiency to increase are proposed. New type of high-performance computer systems, which are named self-configurable FPGA-based computer systems and perform information processing according to this improved method, is proposed. The structure of self-configurable FPGA-based computer systems, rules of application of computer software and hardware means, which are necessary for these systems implementation, are described and their execution time characteristics are estimated. The directions for further works are discussed.


References | Cited By  «-- Click to see who has cited this paper

[1] Scott Hauck, Andre DeHon. "Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation". Morgan Kaufmann, 2008. - 944 p.

[2] Melnyk A., Melnyk V. "Personal Supercomputers: Architecture, Design, Application". - Lviv National Polytechnic University Publishing, 2013. - 516 p.

[3] Christophe Bobda. "Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications". - Springer, 2010. - 362 p.

[4] T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk and P. Cheung. Reconfigurable Computing: Architectures, Design Methods, and Applications. IEE Proceedings on Computers and Digital Techniques 152 (2) pp.193-207 (2005).
[CrossRef] [Web of Science Times Cited 118] [SCOPUS Times Cited 218]


[5] C-to-Verilog. Cirquit Design Automation. [Online] Available: Temporary on-line reference link removed - see the PDF document

[6] IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666-2011. 9 January 2012. - 638 p.

[7] Handel-C Synthesis Methodology - Mentor Graphics. [Online] Available: Temporary on-line reference link removed - see the PDF document

[8] Catapult LP for a Power Optimized ESL Hardware Realization Flow. [Online] Available: Temporary on-line reference link removed - see the PDF document

[9] DIMETalk. FPGA Development Tools. [Online] Available: Temporary on-line reference link removed - see the PDF document

[10] C-to-FPGA Tools form Impulse Accelerated Technologies. Impulse CoDeveloper C-to-FPGA Tools. [Online] Available: Temporary on-line reference link removed - see the PDF document

[11] ROCCC2.0. Jacquard Computing. [Online] Available: Temporary on-line reference link removed - see the PDF document

[12] A. Melnyk, A. Salo, V. Klymenko, L. Tsyhylyk. Chameleon - system for specialized processors high-level synthesis. Scientific-technical magazine of National Aerospace University "KhAI", Kharkiv, 2009. N5, pp. 189-195.

[13] Chameleon - the System-Level Design Solution. [Online] Available: Temporary on-line reference link removed - see the PDF document

[14] S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau. SPARK: a high-level synthesis framework for applying parallelizing compiler transformations. Proc. International Conference on VLSI Design, January 2003.

[15] Gupta, S., Gupta, R.K., Dutt, N.D., Nicolau, A.: SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Kluwer Academic, Dordrecht (2004).

[16] Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into an integrated processor with reconfigurable logic. Oct, 12 1999: US 5966534.

[17] Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic. Intel Mar, 16 2004: US 6708325.

[18] V. Melnyk, V. Stepanov, Z. Sarajrech. System of load balancing between host computer and reconfigurable accelerator. Proceedings "Computer systems and components" of Tchernivtsi National University. - Tchernivtsi. 2012. T. 3. Ed. 1. pp. 6-16.

[19] Ivor Horton. Beginning Visual C++ 2005. - John Wiley & Sons., 2005. - 1224 p.

[20] DRC Computer Corporation. RPU100-L60 DRC Reconfigurable Processor Unit. A breakthrough in coprocessor technology. [Online] Available: Temporary on-line reference link removed - see the PDF document

[21] H100 Series FPGA Application Accelerators. Version 1.9. September 2008. [Online] Available: Temporary on-line reference link removed - see the PDF document

[22] Celoxica Ltd. RCHTX-XV4 High Performance Computing (HPC) Application Acceleration Board Datasheet. Version 1.0. 2006. [Online] Available: Temporary on-line reference link removed - see the PDF document

[23] Relogix Assembler-to-C translator. [Online] Available: Temporary on-line reference link removed - see the PDF document

[24] Handel-C Language Reference Manual For DK Version 4. Celoxica Limited, 2005. - 348p.

[25] Agility Compiler for SystemC. Electronic System Level Behavioral Design & Synthesis Datasheet. 2005. [Online] Available: Temporary on-line reference link removed - see the PDF document



References Weight

Web of Science® Citations for all references: 118 TCR
SCOPUS® Citations for all references: 218 TCR

Web of Science® Average Citations per reference: 5 ACR
SCOPUS® Average Citations per reference: 8 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references background updated on 2017-02-26 07:16 in 12 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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