Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 0.595
JCR 5-Year IF: 0.661
Issues per year: 4
Current issue: Feb 2018
Next issue: May 2018
Avg review time: 108 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


1,876,459 unique visits
Since November 1, 2009

No robots online now


SCImago Journal & Country Rank

SEARCH ENGINES - Google Pagerank


Anycast DNS Hosting

 Volume 18 (2018)
     »   Issue 1 / 2018
 Volume 17 (2017)
     »   Issue 4 / 2017
     »   Issue 3 / 2017
     »   Issue 2 / 2017
     »   Issue 1 / 2017
 Volume 16 (2016)
     »   Issue 4 / 2016
     »   Issue 3 / 2016
     »   Issue 2 / 2016
     »   Issue 1 / 2016
 Volume 15 (2015)
     »   Issue 4 / 2015
     »   Issue 3 / 2015
     »   Issue 2 / 2015
     »   Issue 1 / 2015
  View all issues  


Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

We have the confirmation Advances in Electrical and Computer Engineering will be included in the Gale database.

Read More »


  4/2012 - 3

A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

WANG, J. See more information about WANG, J. on SCOPUS See more information about WANG, J. on IEEExplore See more information about WANG, J. on Web of Science, LI, Y. See more information about  LI, Y. on SCOPUS See more information about  LI, Y. on SCOPUS See more information about LI, Y. on Web of Science, LI, H. See more information about LI, H. on SCOPUS See more information about LI, H. on SCOPUS See more information about LI, H. on Web of Science
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (637 KB) | Citation | Downloads: 461 | Views: 4,647

Author keywords
Network-on-Chip, Semi Markov process, modeling, queuing theory, simulation

References keywords
chip(12), network(11), design(11), systems(8), performance(8), model(6), networks(5), router(4), marculescu(4), circuits(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2012-11-30
Volume 12, Issue 4, Year 2012, On page(s): 19 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2012.04003
Web of Science Accession Number: 000312128400003
SCOPUS ID: 84872775158

Quick view
Full text preview
In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.

References | Cited By  «-- Click to see who has cited this paper

[1] G. Schelle and D. Grunwald, "Exploring FPGA network on chip implementations across various application and network loads," The 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, Sept 8-10, 2008, pp.41-46.

[2] G. Du, D. Zhang, Y. Song, etc. "Scalability study on mesh based network on chip," Pacific-Asia Workshop on Computational Intelliqence and Industrial Application 2008, Wuhan, China, Dec 19-20, 2008, pp. 681-685.
[CrossRef] [SCOPUS Times Cited 4]

[3] J. Liu, L. Zheng, H. Tenhunen, "Interconnect intellectual property for Network-on-Chip," Journal of Systems Architecture, vol(50), pp.65-79, 2004.
[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 35]

[4] R. Marculescu, Y. O. Umit, L. Peh, "Outstanding research problems in noc design: system, microarchitecture, and circuit perspectives". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2009. vol(28), pp. 3-21.
[CrossRef] [Web of Science Times Cited 324] [SCOPUS Times Cited 487]

[5] C. Chou, U.Y. Ogras., R. Marculescu. "Energy and performance aware incremental mapping for networks on chip with multiple voltage levels," IEEE transactions on computer-aided design of integrated circuits and systems, vol(27), pp.1866-1879, Oct, 2008.
[CrossRef] [Web of Science Times Cited 84] [SCOPUS Times Cited 131]

[6] P. Lieverse, P. van der Wolf, E. Deprettere, et al. "A methodology for architecture exploration of heterogeneous signal processing systems," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2001, pp. 181-190.
[CrossRef] [Web of Science Times Cited 54] [SCOPUS Times Cited 93]

[7] M. Moadeli, A. Shahrabi, W. Vanderbauwhede, and M. Ould-Khaoua, "An analytical performance model for the spidergon noc". 21st International Conference on Advanced Information Networking and Applications, 2007. Niagara Falls, Canada, pp. 1014-1021. 2007.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 50]

[8] Foroutan, S., Thonnart, Y., Hersemeule, R. and Jerraya, A. "An Analytical Method for Evaluating Network-on-Chip Performance". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Dresden, Germany, pp. 1629-1632. 2010.

[9] T. N. Mudge and H. B. Al-Sadoun, "A Semi-Markov Model for the Performance of Multiple-Bus Systems," IEEE Trans. Computers, vol. 34, no. 10, pp. 934-942, Oct. 1985.
[CrossRef] [Web of Science Times Cited 35]

[10] Y. Zhang, L. Li, S. Yang, etc. "A scalable distributed memory architecture for network on chip," IEEE Asia Pacific conference on circuits and systems, Macao, China. Nov 30-Dec.3, 2008, pp. 1260-1263.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 4]

[11] Y. Gao, Y. Jin, Z. Chang. "Ultra-low latency reconfigurable photonic network on chip architecture based on application pattern," OFC 2009, San Diego, March, 22-26, 2009, pp. 1-3.

[12] E. Salminen, T. Kangas, V. Lahtinen, et al. "Benchmarking mesh and hierarchical bus networks in system-on-chip context," SAMOS 2005. Greece, July 2005, pp. 354 - 363.

[13] T. Huang, U. Y. Ogras, R. Marculescu, "Virtual channels planning for networks-on-chip", International Symposium on Quality Electronic Design, 2007, San Jose, USA. pp. 879-884. 2007.
[CrossRef] [SCOPUS Times Cited 60]

[14] D. Stiliadis and A. Varma, "Latency-rate servers: a general model for analysis of traffic scheduling algorithms," IEEE transactions on networking. vol(1), pp. 111-119, 1996.

[15] M. Fabio Chiussi and Andrea Francini, "Implementing fair queueing in ATM switches-parts 1: a practical methodology for analysis of delay bounds," Global Telecommunication Conference, 1997. London U.K., pp. 509-519.

[16] V. S. Adve and M. K. Vernon, "Performance analysis of mesh interconnection networks with deterministic routing," IEEE Trans. Parallel Distrib.System. vol 3(5), pp.225-246, 1994.
[CrossRef] [Web of Science Times Cited 60] [SCOPUS Times Cited 82]

[17] J. Y. L. Boudec and P. Thiran, Network calculus. vol. 2050. New York: Springer-Verlag, 2001.

[18] C. Wu, Y. Li, Q. Peng. "Microarchitecture design and performance evaluation of NOC router for multi-processor measuring system," Journal of electronic measurement and instrument. vol 5(22): 101-106, 2008.

[19] A. Narasimhan, K. Srinivasan, R. Sridhar, "A high-performance router design for VDSM NoCs," IEEE International SOC Conference. Herndon, VA. 2005, pp. 301 - 304.

[20] P. Beekhuizen, D. Fenteneer and I. Adan, "Analysis of a tandem network model of a single-router," ANNALS OF OPERATIONS RESEARCH, vol 1(162), pp. 19-34, 2008.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 4]

[21] Z. Guz, I. Walter, E. Bolotin, etc. "Efficient link capacity and QoS design for network-on-chip," Design, Automation and Test in Europe, 2006. Munich, Germany. March 6-10, 2006, pp. 1 - 6.

[22] S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," DATE 2004, Paris, France. Feb 16-20, 2004, pp. 896-901.

[23] J. Hu, U. Y. Ogras, R. Marculescu, "Application-specific buffer space allocation for networks-on-chip router design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 12(25), pp. 2919 - 2933, 2006.
[CrossRef] [Web of Science Times Cited 89] [SCOPUS Times Cited 153]

[24] J. Wang, Y. Li, Y. Jiang, "Communication performance analytical model and buffer allocation optimizing algorithm for network-on-chip," Journal of Electronics and Information Technology, vol(31), pp. 1059-1062, 2009.

[25] T. N. Mudge, H. B. Al-Sadoun, and B. A. Makrucki, "Memory-interference model for multiprocessors based on semi-Markov processes". IEE Proceedings E Computers and Digital Techniques, vol 134, pp. 203-214. 1987.
[CrossRef] [Web of Science Times Cited 2]

References Weight

Web of Science® Citations for all references: 689 TCR
SCOPUS® Citations for all references: 1,103 TCR

Web of Science® Average Citations per reference: 27 ACR
SCOPUS® Average Citations per reference: 42 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-03-17 01:13 in 110 seconds.

Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2018
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: