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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  4/2012 - 3

A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

WANG, J. See more information about WANG, J. on SCOPUS See more information about WANG, J. on IEEExplore See more information about WANG, J. on Web of Science, LI, Y. See more information about  LI, Y. on SCOPUS See more information about  LI, Y. on SCOPUS See more information about LI, Y. on Web of Science, LI, H. See more information about LI, H. on SCOPUS See more information about LI, H. on SCOPUS See more information about LI, H. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (637 KB) | Citation | Downloads: 508 | Views: 5,174

Author keywords
Network-on-Chip, Semi Markov process, modeling, queuing theory, simulation

References keywords
chip(12), network(11), design(11), systems(8), performance(8), model(6), networks(5), router(4), marculescu(4), circuits(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2012-11-30
Volume 12, Issue 4, Year 2012, On page(s): 19 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2012.04003
Web of Science Accession Number: 000312128400003
SCOPUS ID: 84872775158

Abstract
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Full text preview
In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.


References | Cited By  «-- Click to see who has cited this paper

[1] G. Schelle and D. Grunwald, "Exploring FPGA network on chip implementations across various application and network loads," The 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, Sept 8-10, 2008, pp.41-46.

[2] G. Du, D. Zhang, Y. Song, etc. "Scalability study on mesh based network on chip," Pacific-Asia Workshop on Computational Intelliqence and Industrial Application 2008, Wuhan, China, Dec 19-20, 2008, pp. 681-685.
[CrossRef] [SCOPUS Times Cited 4]


[3] J. Liu, L. Zheng, H. Tenhunen, "Interconnect intellectual property for Network-on-Chip," Journal of Systems Architecture, vol(50), pp.65-79, 2004.
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[4] R. Marculescu, Y. O. Umit, L. Peh, "Outstanding research problems in noc design: system, microarchitecture, and circuit perspectives". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2009. vol(28), pp. 3-21.
[CrossRef] [Web of Science Times Cited 373] [SCOPUS Times Cited 558]


[5] C. Chou, U.Y. Ogras., R. Marculescu. "Energy and performance aware incremental mapping for networks on chip with multiple voltage levels," IEEE transactions on computer-aided design of integrated circuits and systems, vol(27), pp.1866-1879, Oct, 2008.
[CrossRef] [Web of Science Times Cited 111] [SCOPUS Times Cited 151]


[6] P. Lieverse, P. van der Wolf, E. Deprettere, et al. "A methodology for architecture exploration of heterogeneous signal processing systems," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2001, pp. 181-190.
[CrossRef] [Web of Science Times Cited 64] [SCOPUS Times Cited 102]


[7] M. Moadeli, A. Shahrabi, W. Vanderbauwhede, and M. Ould-Khaoua, "An analytical performance model for the spidergon noc". 21st International Conference on Advanced Information Networking and Applications, 2007. Niagara Falls, Canada, pp. 1014-1021. 2007.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 52]


[8] Foroutan, S., Thonnart, Y., Hersemeule, R. and Jerraya, A. "An Analytical Method for Evaluating Network-on-Chip Performance". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Dresden, Germany, pp. 1629-1632. 2010.
[CrossRef] [SCOPUS Times Cited 33]


[9] T. N. Mudge and H. B. Al-Sadoun, "A Semi-Markov Model for the Performance of Multiple-Bus Systems," IEEE Trans. Computers, vol. 34, no. 10, pp. 934-942, Oct. 1985.
[CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 64]


[10] Y. Zhang, L. Li, S. Yang, etc. "A scalable distributed memory architecture for network on chip," IEEE Asia Pacific conference on circuits and systems, Macao, China. Nov 30-Dec.3, 2008, pp. 1260-1263.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 7]


[11] Y. Gao, Y. Jin, Z. Chang. "Ultra-low latency reconfigurable photonic network on chip architecture based on application pattern," OFC 2009, San Diego, March, 22-26, 2009, pp. 1-3.

[12] E. Salminen, T. Kangas, V. Lahtinen, et al. "Benchmarking mesh and hierarchical bus networks in system-on-chip context," SAMOS 2005. Greece, July 2005, pp. 354 - 363.
[CrossRef] [SCOPUS Times Cited 2]


[13] T. Huang, U. Y. Ogras, R. Marculescu, "Virtual channels planning for networks-on-chip", International Symposium on Quality Electronic Design, 2007, San Jose, USA. pp. 879-884. 2007.
[CrossRef] [SCOPUS Times Cited 63]


[14] D. Stiliadis and A. Varma, "Latency-rate servers: a general model for analysis of traffic scheduling algorithms," IEEE transactions on networking. vol(1), pp. 111-119, 1996.
[CrossRef]


[15] M. Fabio Chiussi and Andrea Francini, "Implementing fair queueing in ATM switches-parts 1: a practical methodology for analysis of delay bounds," Global Telecommunication Conference, 1997. London U.K., pp. 509-519.

[16] V. S. Adve and M. K. Vernon, "Performance analysis of mesh interconnection networks with deterministic routing," IEEE Trans. Parallel Distrib.System. vol 3(5), pp.225-246, 1994.
[CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 85]


[17] J. Y. L. Boudec and P. Thiran, Network calculus. vol. 2050. New York: Springer-Verlag, 2001.
[CrossRef]


[18] C. Wu, Y. Li, Q. Peng. "Microarchitecture design and performance evaluation of NOC router for multi-processor measuring system," Journal of electronic measurement and instrument. vol 5(22): 101-106, 2008.

[19] A. Narasimhan, K. Srinivasan, R. Sridhar, "A high-performance router design for VDSM NoCs," IEEE International SOC Conference. Herndon, VA. 2005, pp. 301 - 304.
[CrossRef]


[20] P. Beekhuizen, D. Fenteneer and I. Adan, "Analysis of a tandem network model of a single-router," ANNALS OF OPERATIONS RESEARCH, vol 1(162), pp. 19-34, 2008.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 5]


[21] Z. Guz, I. Walter, E. Bolotin, etc. "Efficient link capacity and QoS design for network-on-chip," Design, Automation and Test in Europe, 2006. Munich, Germany. March 6-10, 2006, pp. 1 - 6.

[22] S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," DATE 2004, Paris, France. Feb 16-20, 2004, pp. 896-901.

[23] J. Hu, U. Y. Ogras, R. Marculescu, "Application-specific buffer space allocation for networks-on-chip router design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 12(25), pp. 2919 - 2933, 2006.
[CrossRef] [Web of Science Times Cited 100] [SCOPUS Times Cited 163]


[24] J. Wang, Y. Li, Y. Jiang, "Communication performance analytical model and buffer allocation optimizing algorithm for network-on-chip," Journal of Electronics and Information Technology, vol(31), pp. 1059-1062, 2009.

[25] T. N. Mudge, H. B. Al-Sadoun, and B. A. Makrucki, "Memory-interference model for multiprocessors based on semi-Markov processes". IEE Proceedings E Computers and Digital Techniques, vol 134, pp. 203-214. 1987.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]




References Weight

Web of Science® Citations for all references: 817 TCR
SCOPUS® Citations for all references: 1,328 TCR

Web of Science® Average Citations per reference: 31 ACR
SCOPUS® Average Citations per reference: 51 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2020-11-22 17:34 in 128 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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