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Static Test Compaction for VLSI Tests An Evolutionary ApproachLOGOFATU, D.
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evolutionary algorithms, digital circuit design, test compaction problem, set coverage problem, test generation, greedy algorithm, optimization, don't care value
algorithms(11), drechsler(6), test(5), logofatu(5), genetic(5), vlsi(4), systems(4), problems(4), design(4), data(4)
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About this article
Date of Publication: 2008-06-02
Volume 8, Issue 2, Year 2008, On page(s): 49 - 53
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2008.02009
Web of Science Accession Number: 000264815000009
SCOPUS ID: 77955593111
The test compaction is one of most important requirement regarding the large scale integration (LSI) testing. The overall cost of a VLSI circuit's testing depends on the length of its test sequence; therefore the reduction of this sequence, keeping the coverage of error prone points, will lead to a reduction of used resources in the testing process. This problem is NP-complete. Consequently an optimal algorithm doesn't have applicability in practice. In this paper we describe an evolutionary algorithm (GATC) and we introduce the term of compaction factor (cf), i.e. the expected percentage of compacted test sequence. GATC provides in praxis better results than a greedy approach (GR) for many configurations. This improvement comes from the freedom to merge randomly pairs of compatible tests for different candidates to solution and keeps the ones with more Don't care positions, thus there is an increased probability to find for them compatible tests in the next stage. Also the C++ implementation was optimized, using compact data structures and the Standard Template Library.
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