B. S. Kirei, V.-I.-M. Chereja, S. Hintea, M. D. Topa, "PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits," Advances in Electrical and Computer Engineering, vol.19, no.1, pp.9-16, 2019, doi:10.4316/AECE.2019.01002
Citation Format:
AECE
Elsevier
Harvard
IEEE
Oxford
Springer
Wiley