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Expansible Network-on-Chip ArchitecturePIRES, I. L. P. , ALVES, M. A. Z. , ALBINI, L. C. P.
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computer architecture, multiprocessor interconnection, system-on-chip, reconfigurable architectures, wireless networks
chip(11), parallel(9), network(8), architecture(6), systems(5), performance(5), circuits(5), specification(4), multi(4), isscc(4)
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About this article
Date of Publication: 2018-05-31
Volume 18, Issue 2, Year 2018, On page(s): 61 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.02008
Web of Science Accession Number: 000434245000008
SCOPUS ID: 85047879531
Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the processing elements. However, the communication outside the chip commonly uses high performance links which have the entire communication protocol stack overhead. This paper introduces the Expansible NoC concept and architecture, which is formed by wired and wireless NoC components in order to provide a low overhead interconnection for intra-chip and inter-chip communication. ENoC couples both networks with the same simplified protocol, enabling the transmission of parallel messages directly in the NoC level. The ability of identifying new communicant on-the-fly increases its flexibility, expanding the system boundaries every time a new system is connected. The ENoC inter-chip wireless link reaches short distances working at 60 GHz with Orthogonal Frequency Division Multiplexing with Quadrature Amplitude Modulation, enabling high bandwidth communication for systems inside a single cluster rack. Experimental evaluations were performed using the Noxim simulator executing computational fluid dynamics benchmark applications. Results show that the proposed architecture improves up to 38% the performance when compared to the newest related work.
|References|||||Cited By «-- Click to see who has cited this paper|
| L. Benini and G. D. Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, pp. 70-78, 2002. |
[CrossRef] [Web of Science Times Cited 1632] [SCOPUS Times Cited 2818]
 S. Deb, A. Ganguly, P. P. Pande, B. Belzer and D. Heo, "Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges," IEEE Journal on Emerging and Selected Topics in Circuits and Systems - (JETCAS), vol. 2, no. 2, pp. 228-239, 2012.
[CrossRef] [Web of Science Times Cited 145] [SCOPUS Times Cited 201]
 J. Howard et al., "A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS," in 2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, pp. 108-109.
[CrossRef] [SCOPUS Times Cited 480]
 H. C. de Freitas, L. M. Schnorr, M. A. Z. Alves, and P. O. A. Navaux, "Impact of Parallel Workloads on NoC Architecture Design," in 18th Euromicro Conference on Parallel, Distributed and Network-based Processing - (PDP), 2010, pp. 551-555.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 10]
 D. Mangano and I. A. Urzi, "System for Designing Network-on-Chip Interconnect Arrangements," US Patent App. 14/940,026, 2016.
 B. A. Floyd, C.-M. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, 2002.
[CrossRef] [Web of Science Times Cited 210] [SCOPUS Times Cited 269]
 M. F. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S. Tam, "CMP Network-on-Chip Overlaid with Multi-band RF-interconnect," in IEEE 14th International Symposium on High Performance Computer Architecture - (HPCA), 2008, pp. 191-202.
[CrossRef] [SCOPUS Times Cited 205]
 M. S. Shamim, J. Muralidharan, and A. Ganguly, "An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links," in Proceedings of the 9th International Symposium on Networks-on-Chip - (NOCS), New York, NY, USA, 2015, p. 2:1-2:8.
[CrossRef] [SCOPUS Times Cited 9]
 M. S. Shamim, N. Mansoor, R. S. Narde, V. Kothandapani, A. Ganguly, and J. Venkataraman, "A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems," IEEE Transactions on Computers - (TC), vol. 66, no. 3, pp. 389-402, 2017.
[CrossRef] [Web of Science Times Cited 28] [SCOPUS Times Cited 41]
 D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, and W. Rayess, "A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors," IEEE Transactions on Parallel and Distributed Systems - (TPDS), vol. 26, no. 12, pp. 3289-3302, 2015.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 39]
 WirelessHD Consortium, "WirelessHD Specification Version 1.1 Overview," Specification. California, USA, 2010.
 R. C. Daniels, J. N. Murdock, T. S. Rappaport, and R. W. Heath, "60 GHz Wireless: Up Close and Personal," IEEE Microwave Magazine - (MMM), vol. 11, no. 7, pp. 44-50, 2010.
[CrossRef] [Web of Science Times Cited 148] [SCOPUS Times Cited 170]
 T. S. Rappaport, Wireless Communications: Principles and Practice. Prentice Hall PTR, 2002.
 C. J. Hansen, "WiGiG: Multi-gigabit wireless communications in the 60 GHz band," IEEE Wireless Communications - (MWC), vol. 18, no. 6, pp. 6-7, 2011.
[CrossRef] [Web of Science Times Cited 115] [SCOPUS Times Cited 134]
 M. Rohling, T. May, K. Bruninghaus, and R. Grunheid, "Broad-band OFDM radio transmission for multimedia applications," Proceedings of the IEEE, vol. 87, no. 10, pp. 1778-1789, 1999.
[CrossRef] [Web of Science Times Cited 100] [SCOPUS Times Cited 143]
 H. Yin and S. Alamouti, "OFDMA: A Broadband Wireless Access Technology," in IEEE Sarnoff Symposium - (SARNOF), 2006, pp. 1-4.
[CrossRef] [SCOPUS Times Cited 86]
 D. J. Law, A. Healey, P. Anslow, S. B. Carlson, V. Maguire, and M. Hajduczenia, "IEEE Standard for Ethernet," IEEE Computer Society, Section One, 2015.
 WIFI Alliance, "60 GHz Technical Specification," WiFi Alliance, Version 1.0, 2016.
 Infiniband TA, "InfiniBand Architecture Specification Volume 1," InfiniBand Trade Association, Release 1.1, 2002.
 C. A. Zeferino and A. A. Susin, "SoCIN: a parametric and scalable network-on-chip," in 16th Symposium on Integrated Circuits and Systems Design - (SBCCI), 2003, pp. 169-174.
[CrossRef] [Web of Science Times Cited 93] [SCOPUS Times Cited 155]
 M. Frumkin, H. Jin, and J. Yan, "Implementation of NAS Parallel Benchmarks in High Performance Fortran," NASA, 1998.
 V. Catania, A. Mineo, S. Monteleone, M. Palesi, and D. Patti, "Noxim: An open, extensible and cycle-accurate network on chip simulator," in IEEE 26th International Conference on Application-specific Systems, Architectures and Processors - (ASAP), 2015, pp. 162-163.
[CrossRef] [SCOPUS Times Cited 146]
 R. F. V. der Wijngaart and H. Jin, "NAS Parallel Benchmarks, Multi-Zone Versions," NASA, 2003.
 D. Bailey, T. Harris, W. Saphir, R. F. V. der Wijngaart, A. Woo, and M. Yarrow, "The NAS parallel benchmarks 2.0," NASA, 1995.
 M. Diener, E. H. M. Cruz, L. L. Pilla, F. Dupros, and P. O. A. Navaux, "Characterizing communication and page usage of parallel applications for thread and data mapping," Journal of Performance Evaluation - (JPEVA), vol. 88, pp. 18-36, 2015.
[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 32]
 H. Krichene, M. Baklouti, P. Marque, J. L. Dekeyser, and M. Abid, "SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC," in 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing - (PDP), 2016, pp. 759-762.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2]
 M. Yuffe, E. Knoll, M. Mehalel, J. Shor, and T. Kurts, "A fully integrated multi-CPU, GPU and memory controller 32nm processor," in 2011 IEEE International Solid-State Circuits Conference - (ISSCC), 2011, pp. 264-266.
[CrossRef] [SCOPUS Times Cited 91]
 R. Rajsuman, System-on-a-Chip: Design and Test, 1st ed. Norwood, MA, USA: Artech House, Inc., 2000.
 S. Saini et al., "An early performance evaluation of many integrated core architecture based sgi rackable computing system," in International Conference for High Performance Computing, Networking, Storage and Analysis - (SC), 2013, pp. 1-12.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 17]
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