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Stefan cel Mare
University of Suceava
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Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  2/2018 - 3

A Computationally Efficient Pipelined Architecture for 1D/2D Lifting Based Forward and Inverse Discrete Wavelet Transform for CDF 5/3 Filter

CEKLI, S. See more information about CEKLI, S. on SCOPUS See more information about CEKLI, S. on IEEExplore See more information about CEKLI, S. on Web of Science
 
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Download PDF pdficon (1,647 KB) | Citation | Downloads: 896 | Views: 3,133

Author keywords
digital systems, discrete wavelet transforms, multiprocessing systems, pipeline processing, programmable logic arrays

References keywords
wavelet(33), transform(20), lifting(16), architecture(14), discrete(13), systems(12), circuits(10), signal(9), processing(9), image(9)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-05-31
Volume 18, Issue 2, Year 2018, On page(s): 17 - 26
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.02003
Web of Science Accession Number: 000434245000003
SCOPUS ID: 85047844169

Abstract
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In this study, a simple lifting based pipeline DWT (Discrete Wavelet Transform) architecture is proposed for the operation of the CDF 5/3 (Cohen-Daubechies-Feauveau 5/3) filter. This scalable architecture is faster and capable of fulfilling the transformation utilizing the parallel processing operation units. The symmetric boundary extension method is used at the signal boundaries to obtain the best result in the case of 1D/2D. The proposed architecture utilizes the hardware resources in a quite efficient way by means of the pipeline technique. The architectural design is constituted by using RTL (Register Transfer Level) design process and coded by the Verilog HDL. The proposed architecture is tested for several 1D/2D inputs to examine its operation. The related architecture is synthesized for the FPGA board to check the results. The reverse operation is fulfilled by using the same structure only by changing the shift amounts of the shifting units. The DWT coefficients are calculated on this architecture for the 1D/2D situation. The hardware resources are used effectively by utilizing the constituted architecture in folded structure in the 2D case. Satisfying results have been obtained when the different numbers of parallel processing units are utilized.


References | Cited By  «-- Click to see who has cited this paper

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References Weight

Web of Science® Citations for all references: 17,247 TCR
SCOPUS® Citations for all references: 24,209 TCR

Web of Science® Average Citations per reference: 421 ACR
SCOPUS® Average Citations per reference: 590 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-04-17 15:56 in 271 seconds.




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