Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 0.800
JCR 5-Year IF: 1.000
SCOPUS CiteScore: 2.0
Issues per year: 4
Current issue: Feb 2024
Next issue: May 2024
Avg review time: 75 days
Avg accept to publ: 48 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

2,529,031 unique visits
1,005,552 downloads
Since November 1, 2009



Robots online now
SemanticScholar
bingbot


SCOPUS CiteScore

SCOPUS CiteScore


SJR SCImago RANK

SCImago Journal & Country Rank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 24 (2024)
 
     »   Issue 1 / 2024
 
 
 Volume 23 (2023)
 
     »   Issue 4 / 2023
 
     »   Issue 3 / 2023
 
     »   Issue 2 / 2023
 
     »   Issue 1 / 2023
 
 
 Volume 22 (2022)
 
     »   Issue 4 / 2022
 
     »   Issue 3 / 2022
 
     »   Issue 2 / 2022
 
     »   Issue 1 / 2022
 
 
 Volume 21 (2021)
 
     »   Issue 4 / 2021
 
     »   Issue 3 / 2021
 
     »   Issue 2 / 2021
 
     »   Issue 1 / 2021
 
 
  View all issues  


FEATURED ARTICLE

Application of the Voltage Control Technique and MPPT of Stand-alone PV System with Storage, HIVZIEFENDIC, J., VUIC, L., LALE, S., SARIC, M.
Issue 1/2022

AbstractPlus






LATEST NEWS

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

Read More »


    
 

  1/2016 - 10

Highly Efficient, Zero-Skew, Integrated Clock Distribution Networks Using Salphasic Principles

PASCA, A. See more information about PASCA, A. on SCOPUS See more information about PASCA, A. on IEEExplore See more information about PASCA, A. on Web of Science, CIUGUDEAN, M. See more information about CIUGUDEAN, M. on SCOPUS See more information about CIUGUDEAN, M. on SCOPUS See more information about CIUGUDEAN, M. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,478 KB) | Citation | Downloads: 806 | Views: 3,215

Author keywords
bi-dimensional clock distribution, loss compensation, salphasic, standing wave, zero-skew

References keywords
clock(28), circuits(25), distribution(13), state(12), solid(12), systems(9), swing(7), jssc(7), signal(6), power(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 69 - 78
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01010
Web of Science Accession Number: 000376995400010
SCOPUS ID: 84960100537

Abstract
Quick view
Full text preview
The design of highly efficient clock distributions for integrated circuits is an active topic of research as there will never be a single solution for all systems. For high performance digital or mixed-signal circuits, achieving zero-skew clock over large areas usually comes with high costs in power requirements and design complexity. The present paper shows an overview of a recently proposed technique for ICs - on-die salphasic clock distribution, introduced by the author for CMOS processes. Initially reported in literature for rack-systems, the present paper shows that further refinements are needed for the concept to be applicable on a silicon die. Based on the formation of a standing wave (intrinsically presenting extended in-phase regions) with a voltage peak at the input (creating a no-load condition), it is shown that any IC implementation must use transmission lines loss compensation techniques to maintain the proper standing wave configuration. Furthermore, the paper shows theoretical solutions and describes practical on-die techniques for pseudo-spherical bidimensional surfaces, which, with the already reported orthogonal and pseudo-orthogonal structures, can be used to distribute with minimal power requirements a zero-skew clock signal, over large silicon areas.


References | Cited By  «-- Click to see who has cited this paper

[1] E. G. Friedman, "Clock distribution networks in synchronous digital integrated circuits," Proceedings of the IEEE, vol. 89, no. 5, pp. 665-692, May 2001.
[CrossRef] [Web of Science Times Cited 282] [SCOPUS Times Cited 361]


[2] E. De Man, M. Schöbinger, "Power Dissipation in the Clock System of highly pipelined ULSI CMOS Circuits", Proceedings of the International Workshop on Low-Power Design, Apr. 1994.

[3] H. Kojima, S. Tanaka, K. Sasaki,"Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry", Symposium on VLSI Circuits, Digest of Technical Papers, pp. 432-435, 1994.
[CrossRef]


[4] H. Kawaguchi, T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998.
[CrossRef] [Web of Science Times Cited 160] [SCOPUS Times Cited 241]


[5] K. D. Boese, A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", Proceedings of the 5th Annual IEEE International ASIC Conference and Exhibit, pp. 17-21, Sep. 1992.
[CrossRef] [SCOPUS Times Cited 141]


[6] G. M. Blair, "Skew-Free Clock Distribution for Standard-Cell VLSI Designs", Proceedings of IEE Circuits, Devices and Systems, vol. 139, no 2, pp 265-268, Apr. 1992.

[7] Y. P. Chen, D. F. Wong, "An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion", Proceedings of European Design and Test Conference 1996 ED&TC 96, pp. 230-236, 11 - 14 March, 1996.
[CrossRef] [Web of Science Times Cited 46] [SCOPUS Times Cited 5]


[8] T. Fischer, J. Desai, B. Doyle, S. Naffziger, B. Patella, "A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor," IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 218-228, Jan. 2006.
[CrossRef] [Web of Science Times Cited 75] [SCOPUS Times Cited 105]


[9] V. Gutnik, A. P. Chandrakasan, "Active GHz clock network using distributed PLLs," IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1553-1560, Nov. 2000.
[CrossRef] [Web of Science Times Cited 56] [SCOPUS Times Cited 66]


[10] H.-A. Tanaka, A. Hasegawa, H. Mizuno, T. Endo, "Synchronizability of distributed clock oscillators," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1271-1278, Sep. 2002.
[CrossRef] [Web of Science Times Cited 23] [SCOPUS Times Cited 21]


[11] A. Carpenter, "Design and Use of High-Speed Transmission Line Links for Global On-Chip Communication", PhD Dissertation, University of Rochester, 2012.

[12] S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, M. Horowitz, "The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor," IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 197-209, Jan. 2006.
[CrossRef] [Web of Science Times Cited 70] [SCOPUS Times Cited 86]


[13] E. Takahashi, Y. Kasai, M. Murakawa, T. Higuchi, "Post-Fabrication Clock-Timing Adjustment Using Genetic Algorithms," IEEE Journal of Solid-State Circuits, vol. 39, no. 4, pp. 643-650, Apr. 2004.
[CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 18]


[14] R.J. Riedlinger, R. Bhatia, L. Biro, B. Bowhill, E. Fetzer, P. Gronowski, T. Grutkowski, "A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers", Digest of Technical Papers, 2011 IEEE International Solid-State Circuits Conference (ISSCC), pp. 84-86, 20-24 February 2011.
[CrossRef] [SCOPUS Times Cited 52]


[15] P. Sedcole, J.S. Wong, P.Y.K. Cheung, "Modelling and compensating for clock skew variability in FPGAs", International Conference on ICECE Technology, 2008, pp. 217-224, 8-10 Dec. 2008.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 7]


[16] T. Susa, M. Murakawa, E. Takahashi, T. Furuya, T. Higuchi, "Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins", 8th International Conference on Hybrid Intelligent Systems, 2008, pp. 907-910, 10-12 Sep. 2008.
[CrossRef] [SCOPUS Times Cited 6]


[17] YS. Kwon, IC. Park, CM. Kyung, "A New Single-Clock Flip-Flop for Half-Swing Clocking", Proceedings of the ASP-DAC '99 Design Automation Conference, Asia and South Pacific, vol. 1, pp. 117 - 120, 18-21 Jan. 1999.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 11]


[18] C. Kim, S.-M. Kang, "A low-swing clock double-edge triggered flip-flop," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 648-652, May 2002.
[CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 72]


[19] D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, T. Sakurai, "Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution", 33rd European Solid State Circuits Conference ESSCIRC 2007, pp. 190 - 193, 11-13 Sep. 2007.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 7]


[20] K. Mohammad, B. Liu, S. Agaian, "Energy efficient swing signal generation circuits for clock distribution networks", IEEE International Conference on Systems, Man and Cybernetics SMC 2009, pp. 3495 - 3498, 11-14 Oct. 2009.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 3]


[21] S. E. Esmaeili, A. J. Al-Kahlili,, G. E. R. Cowan, "Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 8, pp. 1547-1551, Aug. 2012.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 22]


[22] A. J. Drake, K. J. Nowka, T. Y. Nguyen, J. L. Burns, R. B. Brown, "Resonant clocking using distributed parasitic capacitance," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1520-1528, Sep. 2004.
[CrossRef] [Web of Science Times Cited 73] [SCOPUS Times Cited 96]


[23] S. C. Chan, K. L. Shepard, P. J. Restle, "Uniform-phase uniform-amplitude resonant-load global clock distributions," IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 102-109, Jan. 2005.
[CrossRef] [Web of Science Times Cited 51] [SCOPUS Times Cited 68]


[24] F. O'Mahony, C. P. Yue, M. A. Horowitz, S. S. Wong, "A 10-GHz global clock distribution using coupled standing-wave oscillators," IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1813-1820, Nov. 2003.
[CrossRef] [Web of Science Times Cited 100] [SCOPUS Times Cited 121]


[25] M. Shiozaki, M. Sasaki, A. Mori, A. Iwata, H. Ikeda, "20GHz uniform-phase uniform-amplitude standing-wave clock distribution," IEICE Electronics Express, vol. 3, no. 2, pp. 11-16, 2006.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]


[26] V. L. Chi, "Salphasic distribution of clock signals for synchronous systems," IEEE Transactions on Computers, vol. 43, no. 5, pp. 597-602, May 1994.
[CrossRef] [Web of Science Times Cited 60] [SCOPUS Times Cited 71]


[27] V. L. Chi, "Salphasic Distribution of Timing Signals for the Synchronization of Phisically Separated Entities", US patent US5387885, 7 Feb., 1995.

[28] A. Pasca, "Probleme specifice ce apar în retelele de distributie de clock (Specific problems in clock distribution networks)", MSc dissertation, "Politehnica" University, Timisoara, Romania, 2006.

[29] K. Moez, M. Elmasry, "A New Loss Compensation Technique for CMOS Distributed Amplifiers," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 3, pp. 185-189, Mar. 2009.
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 8]


[30] M. Yazgi, A. Toker, B. S. Virdee, "A new negative resistance circuit and an application for loss compensation in a distributed amplifier," Journal of Analog Integrated Circuits and Signal Processing, vol. 60, no. 3, pp. 215-220, Sep. 2009.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 4]


[31] A. Ghadiri, "Design of Active-Based Passive Components for Radio Frequency Applications", PhD Dissertation, University of Alberta, 2011.

[32] M. Bussmann, U. Langmann, "Active compensation of interconnection losses for multi-GHz clock distribution networks," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 11, pp. 790-798, Nov. 1992.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 7]


[33] B. Ravelo, A. Perennec, M. Le Roy, "Application of Negative Group Delay Active Circuits to Reduce the 50% Propagation Delay of RC-Line Model", 12th IEEE Workshop on Signal Propagation on Interconnects, 2008, pp. 1-4, May 2008.
[CrossRef] [SCOPUS Times Cited 14]


[34] B. Ravelo, A. Perennec, M. Le Roy, "Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits", 11th IEEE Workshop on Signal Propagation on Interconnects (SPI'07), May 2007, pp.15-18, 2007.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 13]


[35] A. P. Jose, K. L. Shepard, "Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication," IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1415-1424, Jun. 2007.
[CrossRef] [Web of Science Times Cited 25] [SCOPUS Times Cited 33]


[36] A. Pasca, "Negative Impedance Converter Circuits for Integrated Clock Transmission Lines Loss Compensation", Buletinul stiintific al Universitatii "Politehnica" din Timisoara, seria Electronica si Telecomunicatii, Tom 54(68), Fascicola 1, 2009.

[37] A. Pasca, "Clock Distribution Using a Bi-dimensional Orthogonal Salphasic Structure", Proceedings of the International Conference on Circuits, Systems, Signal Processing, Communications and Computers (CSSCC 2015), pp. 40-47, Viena, 15-17 March 2015.

[38] A. Pasca, "Bi-dimensional Radially-Salphasic (Standing Wave) Clock Distribution", 2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME), pp. 157-162, 23-26 October, 2014.
[CrossRef] [SCOPUS Times Cited 1]




References Weight

Web of Science® Citations for all references: 1,139 TCR
SCOPUS® Citations for all references: 1,661 TCR

Web of Science® Average Citations per reference: 29 ACR
SCOPUS® Average Citations per reference: 43 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-04-18 22:00 in 254 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2024
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: 


DNS Made Easy