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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

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SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  1/2019 - 2

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

KIREI, B. S. See more information about KIREI, B. S. on SCOPUS See more information about KIREI, B. S. on IEEExplore See more information about KIREI, B. S. on Web of Science, CHEREJA, V.-I.-M. See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about  CHEREJA, V.-I.-M. on SCOPUS See more information about CHEREJA, V.-I.-M. on Web of Science, HINTEA, S. See more information about  HINTEA, S. on SCOPUS See more information about  HINTEA, S. on SCOPUS See more information about HINTEA, S. on Web of Science, TOPA, M. D. See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on SCOPUS See more information about TOPA, M. D. on Web of Science
 
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Download PDF pdficon (1,250 KB) | Citation | Downloads: 1,270 | Views: 2,371

Author keywords
logic design, software libraries, power dissipation, logic gates, CMOS integrated circuits

References keywords
power(17), circuits(10), estimation(9), design(7), cmos(7), vhdl(6), systems(5), digital(5), vlsi(4), system(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-02-28
Volume 19, Issue 1, Year 2019, On page(s): 9 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.01002
Web of Science Accession Number: 000459986900002
SCOPUS ID: 85064200214

Abstract
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In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates.


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Cited-By CrossRef

[1] Tuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging, MILIC, M., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 3, Volume 19, 2019.
Digital Object Identifier: 10.4316/AECE.2019.03009
[CrossRef] [Full text]

[2] PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL, Sandor, Kirei Botond, Farcas, Calin Adrian, Topa, Marina Dana, 2020 43rd International Conference on Telecommunications and Signal Processing (TSP), ISBN 978-1-7281-6376-5, 2020.
Digital Object Identifier: 10.1109/TSP49548.2020.9163455
[CrossRef]

[3] Power and Area Estimation of Discrete Filters in CMOS Integrated Circuits, Kirei, Botond Sandor, Farcas, Calin, Topa, Marina Dana, 2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), ISBN 978-83-62065-36-3, 2019.
Digital Object Identifier: 10.23919/SPA.2019.8936762
[CrossRef]

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