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Efficient FPGA Implementation of High-Throughput Mixed Radix Multipath Delay Commutator FFT Processor for MIMO-OFDMDALI, M. , GUESSOUM, A. , GIBSON, R. M. , AMIRA, A. , RAMZAN, N.
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fast fourier transform, field programmable gate arrays, mimo, ofdm, parallel architecture
systems(18), processor(11), ofdm(10), mimo(7), circuits(7), vlsi(6), very(6), tvlsi(6), scale(6), large(6)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 27 - 38
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01005
Web of Science Accession Number: 000396335900005
SCOPUS ID: 85014212241
This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively.
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 A Computationally Efficient Pipelined Architecture for 1D/2D Lifting Based Forward and Inverse Discrete Wavelet Transform for CDF 5/3 Filter, CEKLI, S., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 2, Volume 18, 2018.
Digital Object Identifier: 10.4316/AECE.2018.02003 [CrossRef] [Full text]
 An Automatic Instruction-Level Parallelization of Machine Code, MARINKOVIC, V., POPOVIC, M., DJUKIC, M., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 18, 2018.
Digital Object Identifier: 10.4316/AECE.2018.01004 [CrossRef] [Full text]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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