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A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation StructureCHIPER, D. F. , CRACAN, A. , BURDIA, D.
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discrete transforms, digital integrated circuits, field programmable gate arrays, large scale integration, systolic arrays
systems(17), circuits(15), processing(14), signal(13), systolic(12), discrete(12), transform(10), efficient(10), algorithm(10), vlsi(9)
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About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 75 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01011
Web of Science Accession Number: 000396335900011
SCOPUS ID: 85014197433
In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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