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FACTS & FIGURES

JCR Impact Factor: 0.699
JCR 5-Year IF: 0.674
Issues per year: 4
Current issue: Aug 2018
Next issue: Nov 2018
Avg review time: 82 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2018-Jun-27
Clarivate Analytics published the InCites Journal Citations Report for 2017. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.699, and the JCR 5-Year Impact Factor is 0.674.

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

Read More »


    
 

  1/2015 - 14

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

KAZMI, M. See more information about KAZMI, M. on SCOPUS See more information about KAZMI, M. on IEEExplore See more information about KAZMI, M. on Web of Science, AZIZ, A. See more information about  AZIZ, A. on SCOPUS See more information about  AZIZ, A. on SCOPUS See more information about AZIZ, A. on Web of Science, AKHTAR, P. See more information about  AKHTAR, P. on SCOPUS See more information about  AKHTAR, P. on SCOPUS See more information about AKHTAR, P. on Web of Science, KUNDI, D.-S. See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (780 KB) | Citation | Downloads: 335 | Views: 2,114

Author keywords
buffer storage, convolver, field programmable gate array, image processing, image storage

References keywords
processing(15), fpga(13), systems(11), image(11), time(10), real(10), implementation(7), design(7), vision(6), hardware(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 95 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01014
Web of Science Accession Number: 000352158600014
SCOPUS ID: 84924812669

Abstract
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Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs) are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA) based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs) implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs) are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU). Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps). Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.


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Cited-By CrossRef

[1] A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure, CHIPER, D. F., CRACAN, A., BURDIA, D., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 17, 2017.
Digital Object Identifier: 10.4316/AECE.2017.01011
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Copyright ©2001-2018
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

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