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JCR Impact Factor: 0.800
JCR 5-Year IF: 1.000
SCOPUS CiteScore: 2.0
Issues per year: 4
Current issue: Feb 2024
Next issue: May 2024
Avg review time: 78 days
Avg accept to publ: 48 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

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  1/2015 - 14

 HIGHLY CITED PAPER 

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

KAZMI, M. See more information about KAZMI, M. on SCOPUS See more information about KAZMI, M. on IEEExplore See more information about KAZMI, M. on Web of Science, AZIZ, A. See more information about  AZIZ, A. on SCOPUS See more information about  AZIZ, A. on SCOPUS See more information about AZIZ, A. on Web of Science, AKHTAR, P. See more information about  AKHTAR, P. on SCOPUS See more information about  AKHTAR, P. on SCOPUS See more information about AKHTAR, P. on Web of Science, KUNDI, D.-S. See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on SCOPUS See more information about KUNDI, D.-S. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
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Download PDF pdficon (780 KB) | Citation | Downloads: 902 | Views: 3,852

Author keywords
buffer storage, convolver, field programmable gate array, image processing, image storage

References keywords
processing(15), fpga(13), systems(11), image(11), time(10), real(10), implementation(7), design(7), vision(6), hardware(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-02-28
Volume 15, Issue 1, Year 2015, On page(s): 95 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.01014
Web of Science Accession Number: 000352158600014
SCOPUS ID: 84924812669

Abstract
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Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs) are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA) based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs) implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs) are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU). Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps). Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.


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Cited-By CrossRef

[1] Image normalization in embedded systems, Monteiro, Heron Aragão, Brito, Alisson Vasconcelos de, Melcker, Elmar Uwe Kurt, Journal of Real-Time Image Processing, ISSN 1861-8200, Issue 6, Volume 18, 2021.
Digital Object Identifier: 10.1007/s11554-021-01098-8
[CrossRef]

[2] Resource-Efficient Image Buffer Architecture for Neighborhood Processors, Kazmi, Majida, Aziz, Arshad, Khan, Hashim Raza, Qazi, Saad Ahmed, Stergioulas, Lampros K., IEEE Access, ISSN 2169-3536, Issue , 2020.
Digital Object Identifier: 10.1109/ACCESS.2020.3025344
[CrossRef]

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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