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Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)CUEVAS-FARFAN, E. , MORALES-SANDOVAL, M. , MORALES-REYES, A. , FEREGRINO-URIBE, C. , ALGREDO-BADILLO, I. , KITSOS, P. , CUMPLIDO, R.
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data security, cryptography, public key, algorithm design and analysis, field programmable gate arrays
karatsuba(12), systems(6), reconfigurable(6), ofman(6), efficient(6), multipliers(5), multiplication(5), reduction(4), parallel(4), multiplier(4)
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About this article
Date of Publication: 2013-05-31
Volume 13, Issue 2, Year 2013, On page(s): 3 - 10
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.02001
Web of Science Accession Number: 000322179400001
SCOPUS ID: 84878919037
In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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