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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  2/2011 - 6

 HIGHLY CITED PAPER 

Improving the Delay of Residue-to-Binary Converter for a Four-Moduli Set

MOLAHOSSEINI, A. S. See more information about MOLAHOSSEINI, A. S. on SCOPUS See more information about MOLAHOSSEINI, A. S. on IEEExplore See more information about MOLAHOSSEINI, A. S. on Web of Science
 
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (619 KB) | Citation | Downloads: 817 | Views: 3,572

Author keywords
Residue Number System (RNS), residue-to-binary converter, digital circuits, computer architecture, high-speed computer arithmetic

References keywords
systems(20), residue(19), moduli(16), binary(15), circuits(14), converter(13), efficient(8), converters(7), design(6), vlsi(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2011-05-30
Volume 11, Issue 2, Year 2011, On page(s): 37 - 42
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2011.02006
Web of Science Accession Number: 000293840500006
SCOPUS ID: 79958809141

Abstract
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The residue number system (RNS) is an unconventional number system which can be used to achieve high-performance hardware implementations of special-purpose computation systems such as digital signal processors. The moduli set {2n-1, 2n, 2n+1, 22n+1-1} has been recently suggested for RNS to provide large dynamic range with low-complexity, and enhancing the speed of internal RNS arithmetic circuits. But, the residue-to-binary converter of this moduli set relies on high conversion delay. In this paper, a new residue-to-binary converter for the moduli set {2n-1, 2n, 2n+1, 22n+1-1} using an adder-based implementation of new Chinese remainder theorem-1 (CRT-I) is presented. The proposed converter is considerably faster than the original residue-to-binary converter of the moduli set {2n-1, 2n, 2n+1, 22n+1-1}; resulting in decreasing the total delay of the RNS system.


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Cited-By Clarivate Web of Science

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Cited-By SCOPUS

SCOPUS® Times Cited: 4
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Cited-By CrossRef

[1] Area Efficient Memoryless Reverse Converter for New Four Moduli Set {2n−1,2n−1,2n+1,22n+1−1}, Jaiswal, Ritesh Kumar, Kumar, Raj, Mishra, Ram Awadh, Journal of Circuits, Systems and Computers, ISSN 0218-1266, Issue 05, Volume 27, 2018.
Digital Object Identifier: 10.1142/S0218126618500755
[CrossRef]

[2] Efficient Reverse Converters for 4-Moduli Sets {2 $$^{2n-1}-1$$ 2 n - 1 - 1 , 2 $$^{n}$$ n , 2 $$^{n}+1$$ n + 1 , 2 $$^{n}-1$$ n - 1 } and {2 $$^{2n-1}$$ 2 n - 1 , 2 $$^{2n-1}-1$$ 2 n - 1 - 1 , 2 $$^{n}+1$$ n + 1 , 2 $$^{n}-1$$ n - 1 } Based on CRTs Algorithm, Noorimehr, Mohammad Reza, Hosseinzadeh, Mehdi, Navi, Keivan, Circuits, Systems, and Signal Processing, ISSN 0278-081X, Issue 10, Volume 33, 2014.
Digital Object Identifier: 10.1007/s00034-014-9798-1
[CrossRef]

[3] Efficient reverse converter design for the new four-moduli set {22n, 2n + 1, 2n/2 + 1, 2n/2 – 1}, Siao, Siang-Min, Sheu, Ming-Hwa, Hwang, Yin-Tsung, Wang, Shao-Yu, Journal of the Chinese Institute of Engineers, ISSN 0253-3839, Issue 2, Volume 40, 2017.
Digital Object Identifier: 10.1080/02533839.2017.1294995
[CrossRef]

[4] A parallel architecture for efficient reverse converter using Chinese remainder theorem, Sahare, Vivek Pralhadrao, Rathkanthiwar, S. V., 2015 International Conference on Communications and Signal Processing (ICCSP), ISBN 978-1-4799-8081-9, 2015.
Digital Object Identifier: 10.1109/ICCSP.2015.7322773
[CrossRef]

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