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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
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ROMANIA

Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  1/2017 - 11

A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

CHIPER, D. F. See more information about CHIPER, D. F. on SCOPUS See more information about CHIPER, D. F. on IEEExplore See more information about CHIPER, D. F. on Web of Science, CRACAN, A. See more information about  CRACAN, A. on SCOPUS See more information about  CRACAN, A. on SCOPUS See more information about CRACAN, A. on Web of Science, BURDIA, D. See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on Web of Science
 
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Download PDF pdficon (1,332 KB) | Citation | Downloads: 73 | Views: 107

Author keywords
discrete transforms, digital integrated circuits, field programmable gate arrays, large scale integration, systolic arrays

References keywords
systems(17), circuits(15), processing(14), signal(13), systolic(12), discrete(12), transform(10), efficient(10), algorithm(10), vlsi(9)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 75 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01011
Web of Science Accession Number: 000396335900011

Abstract
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In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.


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References Weight

Web of Science® Citations for all references: 711 TCR
SCOPUS® Citations for all references: 2,796 TCR

Web of Science® Average Citations per reference: 16 ACR
SCOPUS® Average Citations per reference: 64 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-04-23 00:21 in 264 seconds.




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