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Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling PolicyZAGAN, I. , GAITAN, V. G.
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field programmable gate arrays, pipeline processing, architecture, scheduling, operating systems
architecture(8), gaitan(7), time(5), systems(5), real(5), hardware(5)
No common words between the references section and the paper title.
About this article
Date of Publication: 2016-11-30
Volume 16, Issue 4, Year 2016, On page(s): 45 - 50
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.04007
Web of Science Accession Number: 000390675900007
SCOPUS ID: 85007570607
A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
|References|||||Cited By «-- Click to see who has cited this paper|
| G. C. Buttazzo, "Hard Real-Time Computing Systems - Predictable Scheduling Algorithms and Applications," Third edition, pp. 13-30, Springer, 2011. ISBN: 978-1-4614-0675-4
 M. Zimmer, D. Broman, C. Shaver, and E. A. Lee, "FlexPRET: A processor platform for mixed-criticality systems," in 20th IEEE Real-Time and Embedded Technology and Applications Symposium - RTAS, pp. 101-110, Apr. 2014.
[CrossRef] [SCOPUS Times Cited 41]
 W. Stallings, "Computer Organization and Architecture," 10th Edition, pp. 263-272, 2015. ISBN: 978-0134101613
 E. Dodiu, V. G.Gaitan, and A. Graur, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - architecture description", in IEEE 35th Jubilee International Convention on Information and Communication Technology, Electronics and Microelectronics, Croatia, pp. 859-864, 24 May 2012. INSPEC Accession Number: 12865464
 E. Dodiu and V. G. Gaitan, "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - concept and theory of operation," in IEEE EIT International Conference on Electro-Information Technology, Indianapolis, USA, pp. 1-5, May 2012.
[CrossRef] [SCOPUS Times Cited 15]
 V. G. Gaitan, N. C. Gaitan, and I. Ungurean, "CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661-1674, Sept. 2015.
[CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 13]
 [Online] Available: Temporary on-line reference link removed - see the PDF document
 J. Shawash and D. R. Selviah, "Real-Time Nonlinear Parameter Estimation Using the Levenberg-Marquardt Algorithm on Field Programmable Gate Arrays," IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 170-176, Jan. 2013.
[CrossRef] [Web of Science Times Cited 39] [SCOPUS Times Cited 46]
 M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, "FPGA-Based Reconfigurable Control for Fault-Tolerant Back-to-Back Converter Without Redundancy," IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3360-3371, Aug. 2013.
[CrossRef] [Web of Science Times Cited 59] [SCOPUS Times Cited 79]
 M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, "Fault-Tolerant Five-Leg Converter Topology With FPGA-Based Reconfigurable Control," IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2284-2294, Jun. 2013.
[CrossRef] [Web of Science Times Cited 30] [SCOPUS Times Cited 39]
 T. T. Phuong, K. Ohishi, Y. Yokokura, and C. Mitsantisuk, "FPGA-Based High-Performance Force Control System With Friction-Free and Noise-Free Force Observation," IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 994-1008, Feb. 2014.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 39]
 N. C. Gaitan, I. Zagan, and V. G. Gaitan, "Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation," International Journal of Advanced Computer Science and Applications - IJACSA, vol. 6, no. 4, 2015.
 A. Metzner and J. Niehaus, "MSparc: Multithreading in Real-Time Architectures," Journal of Universal Computer Science, vol. 6, no. 10, pp. 1034-1051, 2000.
 J. Kreuzinger, R. Marston, Th. Ungerer, U. Brinkschulte and C. Krakowski, "The Komodo project: thread-based event handling supported by a multithreaded Java microcontroller," in 25th EUROMICRO Conference, Milano, vol. 2, pp. 122-128, 1999.
[CrossRef] [SCOPUS Times Cited 16]
 I. Zagan and V. G. Gaitan, "Schedulability Analysis of nMPRA Processor based on Multithreaded Execution," in 13rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 130-134, May 19-21, 2016.
[CrossRef] [SCOPUS Times Cited 3]
 "MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS32 Architecture," Revision 3.02, Mar. 2011, [Online] Available: Temporary on-line reference link removed - see the PDF document
 D. A. Patterson and J. L. Hennessy, "Computer Organization and Design, Revised Fourth Edition: The Hardware-Software Interface," Fourth Edition, pp. 330-379, 2011. ISBN: 978-0-12-374750-1
 [Online] Available: Temporary on-line reference link removed - see the PDF document
 E. E Moisuc, A. B. Larionescu, and V. G. Gaitan, "Hardware Event Treating in nMPRA," in 12rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 66-69, 15-17 May, 2014.
[CrossRef] [SCOPUS Times Cited 7]
 S. Kelinman and J. Eykholt, "Interrupts as threads," ACM SIGOPS Operating Syst. Rev., vol. 29, no. 2, pp. 21-26, Apr. 1995.
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Stefan cel Mare University of Suceava, Romania
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