Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 0.595
JCR 5-Year IF: 0.661
Issues per year: 4
Current issue: May 2017
Next issue: Aug 2017
Avg review time: 76 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


1,644,353 unique visits
Since November 1, 2009

No robots online now


SCImago Journal & Country Rank

SEARCH ENGINES - Google Pagerank


Anycast DNS Hosting

 Volume 17 (2017)
     »   Issue 2 / 2017
     »   Issue 1 / 2017
 Volume 16 (2016)
     »   Issue 4 / 2016
     »   Issue 3 / 2016
     »   Issue 2 / 2016
     »   Issue 1 / 2016
 Volume 15 (2015)
     »   Issue 4 / 2015
     »   Issue 3 / 2015
     »   Issue 2 / 2015
     »   Issue 1 / 2015
 Volume 14 (2014)
     »   Issue 4 / 2014
     »   Issue 3 / 2014
     »   Issue 2 / 2014
     »   Issue 1 / 2014
  View all issues  


Broken Bar Fault Detection in IM Operating Under No-Load Condition, RELJIC, D., JERKAN, D., MARCETIC, D., OROS, D.
Issue 4/2016



Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

We have the confirmation Advances in Electrical and Computer Engineering will be included in the Gale database.

IoT is a new emerging technology domain which will be used to connect all objects through the Internet for remote sensing and control. IoT uses a combination of WSN (Wireless Sensor Network), M2M (Machine to Machine), robotics, wireless networking, Internet technologies, and Smart Devices. We dedicate a special section of Issue 2/2017 to IoT. Prospective authors are asked to make the submissions for this section no later than the 31st of March 2017, placing "IoT - " before the paper title in OpenConf.

Read More »


  3/2015 - 21

Genetic Synthesis of New Reversible/Quantum Ternary Comparator

DEIBUK, V. See more information about DEIBUK, V. on SCOPUS See more information about DEIBUK, V. on IEEExplore See more information about DEIBUK, V. on Web of Science, BILOSHYTSKYI, A. See more information about BILOSHYTSKYI, A. on SCOPUS See more information about BILOSHYTSKYI, A. on SCOPUS See more information about BILOSHYTSKYI, A. on Web of Science
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,130 KB) | Citation | Downloads: 160 | Views: 829

Author keywords
genetic algorithms, multivalued logic, ternary comparators, reversible logic, quantum computing

References keywords
quantum(22), logic(16), sible(12), circuits(11), multiple(9), ternary(8), khan(7), evolutionary(7), soft(6), genetic(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2015-08-31
Volume 15, Issue 3, Year 2015, On page(s): 147 - 152
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.03021
Web of Science Accession Number: 000360171500021
SCOPUS ID: 84940762198

Quick view
Full text preview
Methods of quantum/reversible logic synthesis are based on the use of the binary nature of quantum computing. However, multiple-valued logic is a promising choice for future quantum computer technology due to a number of advantages over binary circuits. In this paper we have developed a synthesis of ternary reversible circuits based on Muthukrishnan-Stroud gates using a genetic algorithm. The method of coding chromosome is presented, and well-grounded choice of algorithm parameters allowed obtaining better circuit schemes of one- and n-qutrit ternary comparators compared with other methods. These parameters are quantum cost of received reversible devices, delay time and number of constant input (ancilla) lines. Proposed implementation of the genetic algorithm has led to reducing of the device delay time and the number of ancilla qutrits to 1 and 2n-1 for one- and n-qutrits full comparators, respectively. For designing of n-qutrit comparator we have introduced a complementary device which compares output functions of 1-qutrit comparators.

References | Cited By  «-- Click to see who has cited this paper

[1] M. Nielsen, I. Chuang. Quantum Computation and Quantum Information. Cambridge University Press, 2010.

[2] A. De Vos, M. Bose, S.D. Baerdemacker, "Reversible computation, quantum computation, and computer architectures in between", J. Multiple-Valued Logic and Soft Comput., vol. 18, no. 1, pp. 67-81, 2012.

[3] A. Muthukrishnan, C. R. Stroud, Jr., "Multivalued logic gates for quantum computation," Physical Review A, vol. 62, no. 5, pp. 052309/1-8, 2000.
[CrossRef] [Web of Science Times Cited 135] [SCOPUS Times Cited 45]

[4] A. B. Klimov, R. Guzman, J. C. Retamal, C. Saavedra, "Qutrit quantum computer with trapped ions," Physical Review A, vol. 67, no. 6, 062313/1-7, 2003.
[CrossRef] [Web of Science Times Cited 78]

[5] D. McHugh, J. Twamley, "Trapped-ion qutrit spin molecule quantum computer", New J. Physics, vol. 7, No. 1, pp. 174/1-9,2005.

[6] V. G. Deibuk. I.M. Yuriychuk, R.I. Yuriychuk, "Spin model of full adder on Peres gates," Int. J. Computing, vol. 11, no. 3, pp. 282-292, 2012.

[7] D. M. Miller, M. A. Thornton. Multiple Valued Logic: Concepts and Representations. Morgan & Claypool Publishers, 2008.

[8] M. Lukac, M. Perkowski, H. Goi, M. Pivtoraiko, C. H. Yu, K. Chung, H. Jee, B-G. Kim, Y-D. Kim, "Evolutionary approach to Quantum and Reversible Circuits synthesis," Artificial Intelligence Review, vol. 20, no. 3-4, pp. 361-417, 2003.
[CrossRef] [Web of Science Times Cited 35] [SCOPUS Times Cited 42]

[9] D. M. Miller, D. Maslov, G. W. Dueck, "Synthesis of quantum multiple-valued circuits", J. Multiple-Valued Logic and Soft Comput., vol. 12, no. 5-6, pp. 431-450, 2006.

[10] D. M. Miller, R. Wille, R. Drechsler, "Reducing reversible circuit cost by adding lines", J. Multiple-Valued Logic and Soft Comput., vol. 19, no. 1-3, pp. 185-201, 2012.

[11] M. Lukac M. Perkowski and M. Kameyama, "Evolutionary quantum logic synthesis of boolean reversible logic circuits embedded in ternary quantum space using structural restrictions", in Proc. IEEE Congress on Evolutionary Computation (CEC 2010), Barcelona, Spain, 18-23 July 2010, pp. 1-8.
[CrossRef] [SCOPUS Times Cited 12]

[12] M. H. A. Khan, M. A. Perkowski, M. R. Khan, and P. Kerntopf, "Ternary GFSOP minimization using Kronecker Decision Diagrams and their synthesis with quantum cascades," J. Multiple-Valued Logic and Soft Comput., vol. 11, no. 5-6, pp. 567-602, 2005.

[13] R. Khanom, T. Kamal, M. H. A. Khan, "Genetic algorithm based synthesis of ternary reversible / quantum circuits," in Proc. 11th IEEE Int. Conf. on Computer and Information Technology (ICCIT 2008), Khulna, Bangladesh, 25-27 December, 2008, pp. 270-275.
[CrossRef] [SCOPUS Times Cited 7]

[14] X. Li, G. Yang, D. Zheng, "Logic synthesis of ternary quantum circuits with minimal qutrits," J. of Computers, vol. 8, no. 8, pp. 1941-1946, 2013.
[CrossRef] [SCOPUS Times Cited 8]

[15] Y.-M. Di, and H.-R. Wie, "Synthesis of multivalued quantum logic circuits by elementary gates," Physical Review A, vol. 87, no. 1, pp. 012325/1-8, 2013.
[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 13]

[16] S. B. Mandal, A. Chakrabarti and S. Sur-Kolay, "Quantum Ternary Circuit Synthesis Using Projection Operations," J. Multiple-Valued Logic and Soft Comput., vol. 24, no. 1-4, pp. 73-92, 2015.

[17] K. Fazel, M. A. Thornton, and J. E. Rice, "ESOP-based Toffoli gate cascade generation," in Proc. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, (PacRim,2007), Victoria, Canada, 22-24 August, 2007, pp. 206-209.
[CrossRef] [SCOPUS Times Cited 86]

[18] R. S. Zebulum, M. C. Pachecco, M. M. Vellasco. Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms. CRC Press, 2002.

[19] L. Spector. Automatic Quantum Computer Programming: A Genetic Programming Approach. Kluwer Academic Publishers, 2004.

[20] A. E. Eiben, J. E. Smith. Introduction to Evolutionary Computing. Springer-Verlag, 2013.

[21] M. H. A. Khan, "Design of reversible/quantum ternary comparator circuits," Engineering Letters, vol. 16, no. 2, pp. 178-164, 2008.

[22] R. P. Zadeh, M. Haghparast, "A new reversible/quantum ternary comparator," Australian J. Basic and Applied Sciences, vol. 5, no. 12, pp. 2348-2355, 2011.

[23] D. Mukherjee, A. Chakrabarti, D. Bhattacherjee, "Synthesis of quantum circuits using genetic algorithm," Intern. J. of Recent Trends in Engineering, vol. 2, no. 1, pp. 212-216, 2009.

[24] A.I. Khan, N. Nusrat, S.M. Khan, M. Hasan, M.H.A. Khan, "Quantum realization of some ternary circuits using Muthukrishnan-Stroud gates," in Proc. 37th Intern. Symposium on Multiple-Valued Logic, (ISMVL,2007), Oslo, Norway, 13-16 May 2007, pp. 20.
[CrossRef] [SCOPUS Times Cited 10]

[25] R. Wille, R. Drechsler. Toward a Design Flow for Reversible Logic. Springer Science+Business Media B.V., 2010.

[26] M. Lukac, M. Kameyama, M. D. Miller, M. Perkowski, "High speed genetic algorithms in quantum logic synthesis: Low level parallelization vs. representation," J. Multiple-Valued Logic and Soft Comput., vol. 20, no. 1-2, pp. 89-120, 2013.

[27] V. Deibuk, I. Grytsku, "Optimal synthesis of reversible quantum adders using genetic algorithm," Int. J. Computing, vol. 12, no. 1, pp. 32-41, 2013.

[28] F. Z. Hadjam, C. Moraga, "RIMEP2: Evolutionary design of reversible digital circuits," ACM J, on Emerging Technologies in Computing Systems, vol. 11, no. 3, pp. 2348-2355, 2014.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 5]

[29] K. Datta, I. Sengupta, H. Rahaman, and R. Drechsler, "An evolutionary approach to reversible logic synthesis using output permutation," in Proc. IEEE Design and Test Symposium (IDT), Doha, Qatar, 16-18 Dec. 2013, pp. 1-6.
[CrossRef] [SCOPUS Times Cited 2]

[30] J. Jegier, P. Kerntopf, M. Szyprowski, "An approach to constructing reversible multi-qubit benchmarks with provably minimal implementations," in Proc. 13th IEEE Conference on Nanotechnology (IEEE-NANO,2013), Beijing, China, 5-8 Aug. 2013, pp. 99-104.
[CrossRef] [SCOPUS Times Cited 2]

References Weight

Web of Science® Citations for all references: 264 TCR
SCOPUS® Citations for all references: 232 TCR

Web of Science® Average Citations per reference: 9 ACR
SCOPUS® Average Citations per reference: 7 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-06-27 02:06 in 88 seconds.

Note1: Web of Science® is a registered trademark of Thomson Reuters.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2017
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: