Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 0.699
JCR 5-Year IF: 0.674
Issues per year: 4
Current issue: Aug 2018
Next issue: Nov 2018
Avg review time: 82 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


2,070,443 unique visits
Since November 1, 2009

No robots online now


SCImago Journal & Country Rank

SEARCH ENGINES - Google Pagerank


Anycast DNS Hosting

 Volume 18 (2018)
     »   Issue 3 / 2018
     »   Issue 2 / 2018
     »   Issue 1 / 2018
 Volume 17 (2017)
     »   Issue 4 / 2017
     »   Issue 3 / 2017
     »   Issue 2 / 2017
     »   Issue 1 / 2017
 Volume 16 (2016)
     »   Issue 4 / 2016
     »   Issue 3 / 2016
     »   Issue 2 / 2016
     »   Issue 1 / 2016
 Volume 15 (2015)
     »   Issue 4 / 2015
     »   Issue 3 / 2015
     »   Issue 2 / 2015
     »   Issue 1 / 2015
  View all issues  


Clarivate Analytics published the InCites Journal Citations Report for 2017. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.699, and the JCR 5-Year Impact Factor is 0.674.

Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

Read More »


  2/2014 - 14

Addressing Mode Extension to the ARM/Thumb Architecture

KIM, D.-H. See more information about KIM, D.-H. on SCOPUS See more information about KIM, D.-H. on IEEExplore See more information about KIM, D.-H. on Web of Science
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (668 KB) | Citation | Downloads: 258 | Views: 1,901

Author keywords
computer architecture, computer performance, high performance computing, instruction set design, microprocessors

References keywords
embedded(6), thumb(4), registers(4), performance(4), code(4), architecture(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 85 - 88
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02014
Web of Science Accession Number: 000340868100014
SCOPUS ID: 84901834441

Quick view
Full text preview
In this paper, two new addressing modes are introduced to the 16-bit Thumb instruction set architecture to improve performance of the ARM/Thumb processors. Contrary to previous approaches, the proposed approach focuses on the addressing mode of the instruction set architecture. It adopts scaled register offset addressing mode and post-indexed addressing mode from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To provide the encoding space for the new addressing modes, the register fields in the LDM and STM instructions are reduced, which are not frequently executed. Experiments show the proposed extension achieves an average of 7.0% performance improvement for the seven benchmark programs when compared to the 16-bit Thumb instruction set architecture.

References | Cited By  «-- Click to see who has cited this paper

[1] S. Segars, K. Clarke, and L. Goudge, "Embedded control problems, Thumb, and the ARM7TDMI," IEEE Micro, vol. 15, no. 5, pp. 22-30, 1995.
[CrossRef] [Web of Science Times Cited 43] [SCOPUS Times Cited 64]

[2] K. Kissell, MIPS16: High-Density MIPS for the Embedded Market, Silicon Graphics MIPS Group, Technical report, 1997.

[3] S. Furber, ARM system-on-chip architecture, Addison-Wesley, pp. 188-206, 2000.

[4] R. Phelan, Improving ARM Code Density and Performance, ARM Ltd., Technical report, June 2003.

[5] ARM Ltd., ARM Annual Report & Accounts 2013, 2014.

[6] A. Krishnaswamy and R. Gupta, "Efficient Use of Invisible Registers in Thumb Code," Proc. MICRO, 2005, pp. 30-42.

[7] A. Krishnaswamy, R. Gupta, "Dynamic coalescing for 16-bit instructions," ACM Transaction on Embedded Computing System, vol. 4, no. 1, pp. 3-37, 2005.
[CrossRef] [SCOPUS Times Cited 12]

[8] J. H. Lee, S. M. Moon, and H. K. Choi, "Comparison of Bank Change Mechanisms for Banked Reduced Encoding Architectures," Proc. CSE Vol. 2, 2009, pp. 334-341.

[9] J. H. Lee, and J. Park, and S. M. Moon, "Securing More Registers with Reduced Instruction Encoding Architectures," Proc. RTCSA, 2007, pp. 417-425.

[10] Y. -J. Kwon, X. Ma, and H. J. Lee, "PARE: instruction set architecture for efficient code size reduction," IEE Electronics Letters, vol. 35, no. 24, pp. 2098-2099, 1999.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 15]

[11] L. Dong, Z. Ji, G. Gui, and M. Hu, "Multithreading extension for Thumb ISA and decoder support," Proc. EHAC, 2006, pp. 78-81.

[12] X. Xu, C. Clarke, and S. Jones, "High performance code compression architecture for the embedded ARM/THUMB processor," Proc. CF, 2004, pp. 451-456.

[13] H.-H. Chiang, H.-J. Cheng, and Y.-S. Hwang, "Doubling the Number of Registers on ARM Processors," Proc. INTERACT, 2012, pp. 1-8.

[14] H.-J. Cheng, Y.-S. Hwang, R.-G. Chang, and C.-W. Chen, "Trading Conditional Execution for More Registers on ARM Processors," Proc. EUC, 2010, pp. 53-59.

[15] A. M. Fiskiran and R. B. Lee, "Performance Impact of Addressing Modes on Encryption Algorithms," Proc. ICCD, 2001, pp. 542-545.

[16] J. Lee, J. Kim, C. Jang, S. Kim, B. Egger, K. Kim, and S. Han, "FaCSim: A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems," Proc. LCTES, 2007, pp. 89-100.

[17] ARM Ltd., ARM9TDMITM Technical Reference Manual, 2000.

[18] C. Lee, M. Potkonjak, and H. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Proc. MICRO, 1997, pp. 330-335.

[19] M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "Mibench: A free, commercially representative embedded benchmark suite," Proc. IISWC, 2001, pp. 3-14.

[20] J. L. Henning, "SPEC CPU 2000: Measuring CPU performance in the new millennium," IEEE Computer, vol. 33, no. 7, pp. 28-35, 2000.
[CrossRef] [Web of Science Times Cited 191] [SCOPUS Times Cited 522]

References Weight

Web of Science® Citations for all references: 239 TCR
SCOPUS® Citations for all references: 613 TCR

Web of Science® Average Citations per reference: 11 ACR
SCOPUS® Average Citations per reference: 29 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2018-10-18 08:51 in 32 seconds.

Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2018
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: