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JCR Impact Factor: 0.595
JCR 5-Year IF: 0.661
Issues per year: 4
Current issue: May 2017
Next issue: Aug 2017
Avg review time: 78 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
We have the confirmation Advances in Electrical and Computer Engineering will be included in the EBSCO database.

2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

2017-Jan-30
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2016-Dec-17
IoT is a new emerging technology domain which will be used to connect all objects through the Internet for remote sensing and control. IoT uses a combination of WSN (Wireless Sensor Network), M2M (Machine to Machine), robotics, wireless networking, Internet technologies, and Smart Devices. We dedicate a special section of Issue 2/2017 to IoT. Prospective authors are asked to make the submissions for this section no later than the 31st of March 2017, placing "IoT - " before the paper title in OpenConf.

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  4/2013 - 15

Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection

RAM, D. S. H. See more information about RAM, D. S. H. on SCOPUS See more information about RAM, D. S. H. on IEEExplore See more information about RAM, D. S. H. on Web of Science, BHUVANESWARI, M. C. See more information about  BHUVANESWARI, M. C. on SCOPUS See more information about  BHUVANESWARI, M. C. on SCOPUS See more information about BHUVANESWARI, M. C. on Web of Science, UMADEVI, S. See more information about UMADEVI, S. on SCOPUS See more information about UMADEVI, S. on SCOPUS See more information about UMADEVI, S. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (613 KB) | Citation | Downloads: 401 | Views: 1,684

Author keywords
high level synthesis, field programmable gate arrays, power dissipation, genetic algorithms, reconfigurable logic

References keywords
power(11), design(10), vlsi(9), systems(8), optimization(7), level(7), high(7), integration(5), evolutionary(5), very(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 85 - 92
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04015
Web of Science Accession Number: 000331461300015
SCOPUS ID: 84890198448

Abstract
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Full text preview
FPGAs are increasingly being used to implement data path intensive algorithms for signal processing and image processing applications. In High Level Synthesis of Data Flow Graphs targeted at FPGAs, the effect of interconnect resources such as multiplexers must be considered since they contribute significantly to the area and switching power. We propose a binding framework for behavioral synthesis of Data Flow Graphs (DFGs) onto FPGA targets with power reduction as the main criterion. The technique uses a multi-objective GA, NSGA II for design space exploration to identify schedules that have the potential to yield low-power bindings from a population of non-dominated solutions. A greedy constructive binding technique reported in the literature is adapted for interconnect minimization. The binding is further subjected to a perturbation process by altering the register and multiplexer assignments. Results obtained on standard DFG benchmarks indicate that our technique yields better power aware bindings than the constructive binding approach with little or no area overhead.


References | Cited By  «-- Click to see who has cited this paper

[1] D. S. H. Ram, M. C. Bhuvaneswari, S. M. Logesh, "A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths," IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp.290-295, 2011
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 9]


[2] D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu, "A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths, VLSI Design journal, vol 2012.
[CrossRef] [SCOPUS Times Cited 9]


[3] K. Deb, A. Pratap, S. Agarwal, T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Transactions on Evolutionary Computation, vol.6, no.2, pp.182-197, 2002
[CrossRef] [Web of Science Times Cited 9886] [SCOPUS Times Cited 14368]


[4] K. Deb, "Multi-objective optimization using evolutionary algorithms," John Wiley and Sons, 2003

[5] V. Krishnan, S. Katkoori, A genetic algorithm for the design space exploration of datapaths during high-level Synthesis," IEEE Transactions on Evolutionary Computation, vol.10, no.3, pp. 213- 229 2006
[CrossRef] [Web of Science Times Cited 33] [SCOPUS Times Cited 69]


[6] E. Casseau, B. Le Gal, "High-level synthesis for the design of FPGA-based signal processing systems," International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS'09, pp.25-32, 2009

[7] C. Y. Huang, Y. S. Chen, Y. L. Lin, Y. C. Hsu, "Data path allocation based on bipartite weighted matching," Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC '90, pp 499-504, 1990
[CrossRef]


[8] Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose, "GABIND: A GA approach to allocation and binding for the high-level synthesis of data paths," Very Large Scale Integration (VLSI) Systems, vol 8 no. 6, pp 747-750, 2000

[9] X. Tang, T. Jiang, A. Jones, and P. Banerjee, "Behavioral synthesis of data-dominated circuits for minimal energy implementation," Proceedings of the International Conference on VLSI Design, pp 267-273, 2005.

[10] N. Chabini, W. Wolf, "Unification of scheduling, binding and retiming to reduce power consumption under timings and resources constraints," Very Large Scale Integration (VLSI) Systems, vol.13, no. 10, pp. 1113-1126, 2005.

[11] A. K. Murugavel, N. Ranganathan, "A game theoretic approach for power optimization during behavioral synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1031-1043, 2003.
[CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 14]


[12] D. Chen, J. Cong, Y. Fan, L. Wan, "LOPASS: A Low-power architectural synthesis system for FPGAs with interconnect estimation and optimization," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.4, pp.564-577, 2010
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 19]


[13] A. A. Del Barrio, S. O. Memik, M. C. Molina, J. M. Mendias, R. Hermida, "A fragmentation aware high-level synthesis flow for low power heterogeneous datapaths," Integration, the VLSI journal,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Record]


[14] D. Bekiaris, E. S. Xanthopoulos, G. Economakos, D. Soudris, "Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments," International workshop on communication centric system on chip ReCoSoC, pp 1-8, 2012

[15] D. Bekiaris, G. Economakos, E.S. Xanthopoulos, D. Soudris, "Low-power reconfigurable component utilization in a high-level synthesis flow," International Conference on Reconfigurable computing and FPGAs, pp 428-433, 2011

[16] C. Wolinski, K. Kuchcinski, E. Raffin, F. Charot, "Architecture-driven synthesis of reconfigurable cells," Euromicro conference on digital system design/architecture, methods and tools, pp 531-538, 2009

[17] R. Tessier, "Power-efficient RAM mapping algorithms for FPGA embedded memory blocks," IEEE Transactions on CAD of Integrated Circuits and Systems, vol 26, no.2, 2007

[18] F. Ferrandi, P. L. Lanzi, G. Palermo, C. Pilato, D. Sciuto, A. Tumeo, "An evolutionary approach to area-time optimization of FPGA designs," International Conference on Embedded Systems: Architectures, Modeling and Simulation, IC-SAMOS, pp 145-152, , 2007

[19] J. M. Chang, M. Pedram, "Register allocation and binding for low power," Proceedings of ACM/IEEE Design Automation Conference, DAC '95, pp 29-35, 1995

[20] E. Kursun, R. Mukherjee, S. O. Memik," Early quality assessment for low power behavioral synthesis. Journal of Low Power Electronics, vol 1, no.3, pp 1-13, 2005
[CrossRef]


[21] S. H. Gerez, "Algorithms for VLSI design automation, John Wiley and Sons, 2000

[22] D. Chen, J. Cong, "Register binding and port assignment for multiplexer optimization. In: ASP-DAC '04 Proceedings of the 2004 Asia and South Pacific Design Automation Conference, pp. 68-73, 2004

[23] R. K. Ahuja, T. L. Magnanti, J.B. Orlin, "Network Flows: Theory, Algorithms, and Applications," Prentice-Hall, Englewood Cliffs, NJ, 1993.

[24] Mediabench benchmark suite Available [Online] Available: Temporary on-line reference link removed - see the PDF document

[25] Xpower estimator user guide [Online] Available: Temporary on-line reference link removed - see the PDF document



References Weight

Web of Science® Citations for all references: 9,948 TCR
SCOPUS® Citations for all references: 14,488 TCR

Web of Science® Average Citations per reference: 383 ACR
SCOPUS® Average Citations per reference: 557 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-06-22 01:09 in 64 seconds.




Note1: Web of Science® is a registered trademark of Thomson Reuters.
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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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