|4/2013 - 12|
Low Complexity Approach for High Throughput Belief-Propagation based Decoding of LDPC CodesBELEAN, B. , BORDA, M. , BOT, A. , NEDEVSCHI, S.
|Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (623 KB) | Citation | Downloads: 302 | Views: 1,949|
LDPC decoder, decoding algorithms, low-complexity, hardware implementations, belief propagation
ldpc(17), codes(15), decoding(8), systems(6), decoder(5), turbo(4), communications(4), architecture(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 69 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04012
Web of Science Accession Number: 000331461300012
SCOPUS ID: 84890249314
The paper proposes a low complexity belief propagation (BP) based decoding algorithm for LDPC codes. In spite of the iterative nature of the decoding process, the proposed algorithm provides both reduced complexity and increased BER performances as compared with the classic min-sum (MS) algorithm, generally used for hardware implementations. Linear approximations of check-nodes update function are used in order to reduce the complexity of the BP algorithm. Considering this decoding approach, an FPGA based hardware architecture is proposed for implementing the decoding algorithm, aiming to increase the decoder throughput. FPGA technology was chosen for the LDPC decoder implementation, due to its parallel computation and reconfiguration capabilities. The obtained results show improvements regarding decoding throughput and BER performances compared with state-of-the-art approaches.
|References|||||Cited By «-- Click to see who has cited this paper|
| R. G. Gallager, "Low-Density Parity-Check Codes," IRE Transmission Information Theory, vol. 8, pp. 21-28, Jan. 1962. |
[CrossRef] [SCOPUS Times Cited 3910]
 Sangmin Kim, Gerald E. Sobelman, and Hanho Lee, "A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes," IEEE Transactions on VLSI systems, 2011.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 23]
 Steffen Kunze, Emil Matus and Gerhard P. Fettweis, ASIP Decoder Architecture for Convolutional and LDPC Codes, IEEE Int. Symposium on Circuits and Systems, ISCAS 2009.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 10]
 Z. Zhang, et al., "Design of LDPC Decoders for Improved Low Error Rate Performance: Quantization and Algorithm Choices," IEEE Trans. on Wireless Comm., 8(11), pp. 3258-3268, 2009.
[CrossRef] [Web of Science Times Cited 34] [SCOPUS Times Cited 59]
 H. Ji, J. Cho, W. Sung , "Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU," Journal of Signal Processing Systems, 64(1), pp 149-159, 2011.
[CrossRef] [Web of Science Times Cited 17] [SCOPUS Times Cited 24]
 G. Falcao, L. Sousa, V. Silva, "Massively LDPC Decoding on Multicore Architectures," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 2, 2011.
[CrossRef] [Web of Science Times Cited 46] [SCOPUS Times Cited 69]
 Houston M, Stanford University, General Purpose Computation on Graphics Processors, 2008.
 J. Su, K. Liu, H. Min, "Hardware Efficient Decoding of LDPC Codes Using Partial-min Algorithms," IEEE Trans. on Consumer Electronics, 52(4), pp. 1463-1468, November 2006.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 6]
 M. Awais, A. Singh, G. Masera, "High Throughput LDPC Decoder for WiMAX (802.16e) Applications," Advances in Computing and Communications, Communications in Computer and Information Science Volume 191, pp 374-385, 2011.
[CrossRef] [SCOPUS Times Cited 3]
 Y. Sun, J. Cavallaro, " Flexible LDPC/Turbo Decoder Architecture," Journal of Signal Processing Systems, 64(1), pp 1-16, 2011.
[CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 21]
 Matthias Alles, Timo Vogt, Norbert Wehn, FlexiChaP: A Reconfigurable ASIP for Convolutional, Turbo, and LDPC Code Decoding, International Symposium on Turbo Codes, 2008.
[CrossRef] [Web of Science Times Cited 23] [SCOPUS Times Cited 52]
 Xiaojun Zhang, Yinghong Tian, et al. , An Multi-Rate LDPC Decoder Based on ASIP for DMB-TH, IEEE 8th International Conference on ASIC, pp. 995-998, 2009.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 5]
 F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE Transactions on Information Theory, 47(2), pp. 498-519, February 2001.
[CrossRef] [Web of Science Times Cited 2821] [SCOPUS Times Cited 3751]
 Bernhard M.J. Leiner, LDPC Codes - a brief Tutorial, 2005.
 J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier and X. Hu, "Reduced Complexity Decoding of LDPC Codes," IEEE Transactions on Communications, 53, pp. 1232-1232, 2005.
[CrossRef] [Web of Science Times Cited 422] [SCOPUS Times Cited 579]
 Sunghwan Kim, Min-Ho Janget, et al., "Sequential message-passing decoding of LDPC codes by partitioning check nodes," IEEE Trans. on Communications, 56 (7), pp. 1025-1031, 2008.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 5]
 John R. Barry, Low-Density Parity-Check Codes, Georgia Institute of Tech., October 2001
 Daesun Oh and K. Parhi, "Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes," IEEE Trans. on Circuits and Cystems, 57(1), pp. 105-115, January 2010.
[CrossRef] [Web of Science Times Cited 27]
 C. Jego, P. Adde, C. Leroux, "Full-parallel architecture for turbo decoding of product codes," Electronics Letters, 42(18), pp. 1052-1054, 2006.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 15]
 R. Terebes, "Mobile communication systems. Part one: GSM networks," UTPRES, Cluj-Napoca, 2006, ISBN 978-973-662-221.
 D. Klinc, J. Ha, S. McLaughlin, J. Barros and B. Kwak, "LDPC Codes for Physical Layer Security," IEEE Globecom , 2009.
[CrossRef] [SCOPUS Times Cited 28]
 Q. Huang, S. Pan., M. Zhang and Z. Wang, "A concatenation scheme of LDPC codes and source codes for flash memories," EURASIP Journal on Advances in Signal Processing, Vol. 208, 2012.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 3]
 A. D. Potorac, "Considerations on VoIP Throughput in 802.11 Networks," Advances in Electrical and Computer Engineering, Volume 9, Number 3, 2009.
 E. Puschita, P. Kantor, G. Manuliac, T. Palade, J. Bito, "Enabling Frame-Based Adaptive Video Transmission in a Multilink Environment," Advances in Electrical and Computer Engineering Volume 12, Number 2, 2012.
[CrossRef] [Full Text] [Web of Science Times Cited 1] [SCOPUS Times Cited 3]
 X. Hu, E. Eleftheriou, D. Arnold, A. Dholakia, "Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes", IEEE Globecom Proceedings, 2001.
Web of Science® Citations for all references: 3,447 TCR
SCOPUS® Citations for all references: 8,566 TCR
Web of Science® Average Citations per reference: 133 ACR
SCOPUS® Average Citations per reference: 329 ACR
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references updated on 2019-02-13 03:57 in 144 seconds.
Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.