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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 644266260
doi: 10.4316/AECE


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  4/2013 - 12

Low Complexity Approach for High Throughput Belief-Propagation based Decoding of LDPC Codes

BELEAN, B. See more information about BELEAN, B. on SCOPUS See more information about BELEAN, B. on IEEExplore See more information about BELEAN, B. on Web of Science, BORDA, M. See more information about  BORDA, M. on SCOPUS See more information about  BORDA, M. on SCOPUS See more information about BORDA, M. on Web of Science, BOT, A. See more information about  BOT, A. on SCOPUS See more information about  BOT, A. on SCOPUS See more information about BOT, A. on Web of Science, NEDEVSCHI, S. See more information about NEDEVSCHI, S. on SCOPUS See more information about NEDEVSCHI, S. on SCOPUS See more information about NEDEVSCHI, S. on Web of Science
 
Click to see author's profile on See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (623 KB) | Citation | Downloads: 251 | Views: 1,351

Author keywords
LDPC decoder, decoding algorithms, low-complexity, hardware implementations, belief propagation

References keywords
ldpc(17), codes(15), decoding(8), systems(6), decoder(5), turbo(4), communications(4), architecture(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 69 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04012
Web of Science Accession Number: 000331461300012
SCOPUS ID: 84890249314

Abstract
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The paper proposes a low complexity belief propagation (BP) based decoding algorithm for LDPC codes. In spite of the iterative nature of the decoding process, the proposed algorithm provides both reduced complexity and increased BER performances as compared with the classic min-sum (MS) algorithm, generally used for hardware implementations. Linear approximations of check-nodes update function are used in order to reduce the complexity of the BP algorithm. Considering this decoding approach, an FPGA based hardware architecture is proposed for implementing the decoding algorithm, aiming to increase the decoder throughput. FPGA technology was chosen for the LDPC decoder implementation, due to its parallel computation and reconfiguration capabilities. The obtained results show improvements regarding decoding throughput and BER performances compared with state-of-the-art approaches.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [SCOPUS Times Cited 3320]


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[CrossRef]




References Weight

Web of Science® Citations for all references: 2,780 TCR
SCOPUS® Citations for all references: 7,145 TCR

Web of Science® Average Citations per reference: 107 ACR
SCOPUS® Average Citations per reference: 275 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2016-12-06 15:46 in 108 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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