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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2017-Jun-14
Thomson Reuters published the Journal Citations Report for 2016. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.595, and the JCR 5-Year Impact Factor is 0.661.

2017-Apr-04
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2017-Feb-16
With new technologies, such as mobile communications, internet of things, and wide applications of social media, organizations generate a huge volume of data, much faster than several years ago. Big data, characterized by high volume, diversity and velocity, increasingly drives decision making and is changing the landscape of business intelligence, from governments to private organizations, from communities to individuals. Big data analytics that discover insights from evidences has a high demand for computing efficiency, knowledge discovery, problem solving, and event prediction. We dedicate a special section of Issue 4/2017 to Big Data. Prospective authors are asked to make the submissions for this section no later than the 31st of May 2017, placing "BigData - " before the paper title in OpenConf.

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2016-Dec-17
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  1/2013 - 2

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

HOO, C.-S. See more information about HOO, C.-S. on SCOPUS See more information about HOO, C.-S. on IEEExplore See more information about HOO, C.-S. on Web of Science, JEEVAN, K. See more information about  JEEVAN, K. on SCOPUS See more information about  JEEVAN, K. on SCOPUS See more information about JEEVAN, K. on Web of Science, GANAPATHY, V. See more information about  GANAPATHY, V. on SCOPUS See more information about  GANAPATHY, V. on SCOPUS See more information about GANAPATHY, V. on Web of Science, RAMIAH, H. See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on Web of Science
 
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Download PDF pdficon (565 KB) | Citation | Downloads: 607 | Views: 2,405

Author keywords
design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization

References keywords
design(14), systems(12), floorplanning(12), vlsi(8), representation(6), circuits(6), algorithm(6), aided(6), scale(5), optimization(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-02-28
Volume 13, Issue 1, Year 2013, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.01002
Web of Science Accession Number: 000315768300002
SCOPUS ID: 84875343057

Abstract
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Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.


References | Cited By  «-- Click to see who has cited this paper

[1] J. M. Lin, Y. W. Chang, and S. P. Lin, "Corner sequence-A p-admissible floorplan representation with a worst case linear-time packing scheme," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 8-12, 2003.
[CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 30]


[2] J. Liu, W. C. Zhong, L. C. Jiao, and X. Li, "Moving block sequence and organizational evolutionary algorithm for general floorplanning with arbitrarily shaped rectilinear blocks," IEEE Transactions on Evolutionary Computation, vol. 12, no. 5, pp. 630-646, 2008.
[CrossRef] [Web of Science Times Cited 17] [SCOPUS Times Cited 29]


[3] S. N. Adya, and I. L. Markov, "Fixed-outline floorplanning: enabling hierarchical design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1120-1135, 2003.
[CrossRef] [Web of Science Times Cited 189] [SCOPUS Times Cited 263]


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[CrossRef] [Web of Science Times Cited 24] [SCOPUS Times Cited 27]


[5] J. M. Lin, and Z. X. Hung, "UFO: Unified convex optimization algorithm for fixed-outline floorplanning considering pre-placed modules," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 7, pp. 1034-1044, 2011.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 8]


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[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 14]


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[CrossRef]


[9] A. Jahanian, and M. S. Zamani, "Metro-on-chip: an efficient physical design technique for congestion reduction," IEICE Electronics Express, vol. 4, no. 16, pp. 510-516, 2007.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]


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[CrossRef] [Web of Science Times Cited 688] [SCOPUS Times Cited 843]


[12] P. N. Guo, T. Takahashi, C. K. Cheng, and T. Yoshimura, "Floorplanning using a tree representation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 281-289, 2001.
[CrossRef] [Web of Science Times Cited 51] [SCOPUS Times Cited 63]


[13] Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu, "B*-trees: A new representation for nonslicing floorplans," in Proceedings of Design Automation Conference, 2000, pp. 458-463. [CiteSeerX]

[14] X. Hong, G. Huang, Y. Cai, S. Dong, C. K. Cheng, and J. Gu, "Corner block list representation and its application to floorplan optimization," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 51, no. 5, pp. 228-233, 2004.
[CrossRef] [Web of Science Times Cited 38] [SCOPUS Times Cited 43]


[15] J. M. Lin, and Y. W. Chang, "TCG: A transitive closure graph-based representation for nonslicing floorplans," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 2, pp. 288-292, 2005.
[CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 30]


[16] J. G. Kim, and Y. D. Kim, "A linear programming-based algorithm for floorplanning in VLSI design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 584-592, 2003.
[CrossRef] [Web of Science Times Cited 24] [SCOPUS Times Cited 33]


[17] C. Luo, M. F. Anjos, and A. Vannelli, "Large-scale fixed-outline floorplanning design using convex optimization techniques," in Proceedings of Asia and South Pacific Design Automation Conference, 2008, pp. 198-203.

[18] S. Alupoaei, and S. Katoori, "Ant Colony System application to macrocell overlap removal," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1118-1123, 2004.
[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 25]


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[20] C.-S. Hoo, H.-C. Yeo, K. Jeevan, V. Ganapathy, H. Ramiah, I.A. Badruddin, "Hierarchical Congregated Ant System for Bottom-up VLSI Placements," Engineering Applications of Artificial Intelligence, vol. 26, no. 1, pp. 584-602, 2013.
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 6]


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[22] J. Rabaey, Gigabyte systems research center 2005.

[23] Y. Pang, C. K. Cheng, and T. Yoshimura, "An enhanced perturbing algorithm for floorplan design using the O-tree representation," in Proceedings of International Symposium on Physical Design, 2000, pp.168-173.
[CrossRef]


[24] G. L. Chen, W. Z. Guo, and Y. Z. Chen, "A PSO-based intelligent decision algorithm for VLSI floorplanning," Soft Computing-A Fusion of Foundations, Methodologies and Applications, vol. 14, no. 12, pp. 1329-1337, 2009.
[CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 40]


[25] J. Chen, and J. Chen, "A hybrid evolution algorithm for VLSI floorplanning," International Conference on Computational Intelligence and Software Engineering, 2010, pp. 1-4.
[CrossRef] [SCOPUS Times Cited 3]




References Weight

Web of Science® Citations for all references: 1,152 TCR
SCOPUS® Citations for all references: 1,471 TCR

Web of Science® Average Citations per reference: 44 ACR
SCOPUS® Average Citations per reference: 57 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2017-10-16 17:05 in 134 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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